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| To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS07-13702-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90520 Series MB90522/523/F523/V520 s DESCRIPTION The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real-time processing. The instruction set of F2MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90520 series has peripheral resources of 8/10-bit A/D converter, a 8-bit D/A converter, UART (SCI), extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), LCD controller/driver. *1: F2MC stands for FUJITSU Flexible Microcontroller. s PACKAGE 120-pin Plastic LQFP 120-pin Plastic QFP (FPT-120P-M05) (FPT-120P-M13) To Top / Lineup / Index MB90520 Series s FEATURES * Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 3 MHz to 16 MHz). The system can be operated by an oscillation sub-clock (rated at 32.768 kHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at VCC of 5.0 V) * Maximum memory space 16 Mbytes * Instruction set optimized for controller applications Ri65data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt function 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 16 channels * Embedded ROM size and types Mask ROM: 64 kbytes/128 kbytes Flash ROM: 256 kbytes Embedded RAM size: 4 kbytes/10 kbytes (mass-produced products) 4 kbytes (flash memory) 6 kbytes (evaluation chip) * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware stand-by mode Clock mode (mode in which other than sub-oscillation and timebase timer are stopped) * Process CMOS technology * I/O port General-purpose I/O ports (CMOS): 53 ports General-purpose I/O ports (via pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 8 ports Total: 85 ports (Continued) 2 To Top / Lineup / Index MB90520 Series (Continued) * Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timers 0, 1: 8-bit x 2 channels or 16-bit x 1 channel 16-bit re-load timers 0, 1: 2 channels * 16-bit I/O timer 16-bit free-run timers 1, 2: 2 channels Input captures 0, 1 (ICU): Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin. Output compares 0, 1 (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value. 8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit x 2 channels) * Extended I/O serial interfaces 0, 1: 1 channel * UART (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used. * DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. * Wake-up interrupt Receives external interrupt requests and generates an interrupt request upon an "L" level input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time: 16.0 s or slower * 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent) Setup time: 12.5 s * Clock timer: 1 channel * LCD controller/driver A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel * Clock output function Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode. 3 To Top / Lineup / Index MB90520 Series s PRODUCT LINEUP Part number Item Classification ROM size RAM size Mass-produced products (mask ROM products) 64 kbytes Mass-produced product (flash ROM product) MB90522 MB90523 MB90F523 MB90V520 Evaluation product None 128 kbytes 6 kbytes The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits CPU functions Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Minimum execution time: 100 ns (at machine clock of 10 MHz) Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 s (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 53 General-purpose I/O ports (via pull-up resistor): 24 General-purpose I/O ports (N-ch open-drain output): 8 Total: 85 Clock synchronized transmission (62.5 kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Conversion precision: 8/10-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 1 (8-bit x 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 s (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 1 (8-bit x 2 channels) Event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel Number of channels: 2 Overflow interrupts Ports UART (SCI) 8/10-bit A/D converter 8/16-bit PPG timers 0, 1 8/16-bit up/down counter/ timers 0, 1 16-bit I/O timer 16-bit freerun timers 1, 2 (Continued) 4 To Top / Lineup / Index MB90520 Series (Continued) Part number Item Output compares 0, 1 (OCU) Input captures 0, 1 (ICU) DTP/external interrupt circuit MB90522 MB90523 MB90F523 MB90V520 16-bit I/O timer Number of channels: 8 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of inputs: 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Number of inputs: 8 Started by an "L" level input. An interrupt generation module for switching tasks Used in real-time operating systems. Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) 8-bit resolution Number of channels: 2 channels Based on the R-2R system Number of common output pins: 4 Number of segment output pins: 32 Number of power supply pins for LCD drive: 4 RAM for LCD indication: 16 bytes Booster for LCD drive: Internal Split resistor for LCD drive: Internal Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by CMOS 3.0 V to 5.5 V 4.0 V to 5.5 V 3.0 V to 5.5 V Wake-up intrrupt Delayed interrupt generation module Extended I/O serial interfaces 0, 1 Timebase timer 8-bit D/A converter LCD controller/driver Watchdog timer Low-power consumption (stand-by) mode Process Power supply voltage for operation* * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz. 5 To Top / Lineup / Index MB90520 Series s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-120P-M05 FPT-120P-M13 : Available x : Not available MB90522 MB90523 MB90F523 Note: For more information about each package, see section "s Package Dimensions." s DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation chips, note the difference between the evaluation chip and the chip actually used. The following items must be taken into consideration. * The MB90V520 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V520, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the deveolpment tool.) * In the MB90522, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. * In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to bank FE and bank FF. 6 To Top / Lineup / Index MB90520 Series s PIN ASSIGNMENT (Top view) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 P31/CKOT P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P36/PG00 P37/PG01 VCC P40/PG10 P41/PG11 P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 PA0/SEG08 PA1/SEG09 PA2/SEG10 PA3/SEG11 PA4/SEG12 PA5/SEG13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P30 VSS P27/ADTG P26/ZIN0/INT7 P25/BIN0 P24/AIN0 P23/IC11 P22/IC10 P21/IC01 P20/IC00 P17/WI7 P16/WI6 P15/WI5 P14/WI4 P13/WI3 P12/WI2 P11/WI1 P10/WI0 P07 P06/INT6 P05/INT5 P04/INT4 P03/INT3 P02/INT2 P01/INT1 P00/INT0 VCC X1 X0 VSS RST MD0 MD1 MD2 HST V3 V2 V1 V0 P97/SEG31 P96/SEG30 P95/SEG29 P94/SEG28 P93/SEG27 P92/SEG26 P91/SEG25 X0A X1A P90/SEG24 P87/SEG23 P86/SEG22 P85/SEG21 P84/SEG20 P83/SEG19 P82/SEG18 P81/SEG17 P80/SEG16 VSS P77/COM3 P76/COM2 PA6/SEG14 PA7/SEG15 VSS C P50/SIN2/AIN1 P51/SOT2/BIN1 P52/SCK2/ZIN1 DVCC DVSS P53/DA0 P54/DA1 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VCC P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7 P74/COM0 P75/COM1 (FPT-120P-M05) (FPT-120P-M13) 7 To Top / Lineup / Index MB90520 Series s PIN DESCRIPTION Pin no. LQFP-120*1 QFP-120*2 92, 93 74, 73 89 to 87 90 86 95 to 101 Pin name X0, X1 X0A, X1A MD0 to MD2 RST HST P00 to P06 Circuit type A B C C C D Function This is a high-speed crystal oscillator pin. This is a low-speed crystal oscillator pin. This is an input pin for selecting operation modes. Connect directly to VCC or VSS. This is external reset request signal. This is a hardware stand-by input pin. This is a general-purpose I/O port. This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid. This is a request input pin of the DTP/external interrupt circuit ch.0 to ch.6. D This is a general-purpose I/O port. This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid. This is a general-purpose I/O port. This function can be set by the port 1 input pull-up resistor setup register (RDR1) for input. For output, however, this function is invalid. This is an I/O pin for wake-up interrupts. E This is a general-purpose I/O port. INT0 to INT6 102 P07 103 to 110 P10 to 17 D WI0 to WI7 111, 112, 113, 114 P20, P21, P22, P23 IC00, IC01, IC10, IC11 115 P24 AIN0 116 P25 BIN0 *1: FPT-120P-M05 *2: FPT-120P-M13 E E This is a trigger input pin for input capture (ICU) 0 and 1. Since this input is used as required for input capture 0 and 1 (ICU) ch.0, ch.01, ch.10 and ch.11 input operation, output by other functions must be suspended except for intentional operation. This is a general-purpose I/O port. This port can be used as count clock A input for 8/16-bit up/down counter/timer 0. This is a general-purpose I/O port. This port can be used as count clock B input for 8/16-bit up/down counter/timer 0. (Continued) 8 To Top / Lineup / Index MB90520 Series Pin no. LQFP-120*1 QFP-120*2 117 Pin name P26 ZIN0 INT7 118 P27 ADTG Circuit type F Function This is a general-purpose I/O port. This port can be used as count clock Z input for 8/16-bit up/down counter/timer 0. This is a request input pin of the DTP/external interrupt circuit ch.7. F This is a general-purpose I/O port. This is external trigger input pin of the 8/10-bit A/D converter. Since this input is used as required for 8/10-bit A/D converter input operation, output by other functions must be suspended except for intentional operation. 120 1 P30 P31 CKOT E E This is a general-purpose I/O port. This is a general-purpose I/O port. This is a clock monitor function output pin. This function is vaild when clock monitor output is enabled. 2 P32 E This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT0 is disabled. This is an event output pins for output compare 0 (OCU) ch.0. This function is valid when output for each channel is enabled. OUT0 3 P33 E This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT1 is disabled. This is an event output pins for output compare 0 (OCU) ch.1. This function is valid when output for each channel is enabled. OUT1 4 P34 E This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT2 is disabled. This is an event output pins for output compare 0 (OCU) ch.2. This function is valid when output for each channel is enabled. OUT2 5 P35 E This is a general-purpose I/O port. This function becomes vaild when waveform output from the OUT3 is disabled. This is an event output pins for output compare 0 (OCU) ch.3. This function is valid when output for each channel is enabled. OUT3 6 P36 E This is a general-purpose I/O port. This function becomes vaild when waveform output from the PG00 is disabled. This is an output pin of 8/16-bit PPG timer 0. This function becomes valid when waveform output from PG00 is enabled. PG00 *1: FPT-120P-M05 *2: FPT-120P-M13 (Continued) 9 To Top / Lineup / Index MB90520 Series Pin no. LQFP-120*1 QFP-120*2 7 Pin name P37 Circuit type E Function This is a general-purpose I/O port. This function becomes vaild when waveform output from the PG01 is disabled. This is an output pin of 8/16-bit PPG timer 0. This function becomes valid when waveform output from PG01 is enabled. PG01 9, 10 P40, P41 D This is a general-purpose I/O port. This function becomes vaild when waveform output from the PG10 and PG11 are disabled. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is an output pin of 8/16-bit PPG timer 1. This function becomes valid when waveform outputs from PG10 and PG11 are enabled. PG10, PG11 11 P42 D This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial data input pin of UART (SCI). Because this input is used as required when UART (SCI) is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. When using other output functions as well, disable output during SIN operation. SIN0 12 P43 D This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial data output pin of UART (SCI). This function becomes valid when serial data output from UART (SCI) is enabled. SOT2 13 P44 D This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial clock I/O pin of UART (SCI). This function becomes valid when serial clock output from UART (SCI) is enabled. SCK0 14 P45 D This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a data input pin for extended I/O serial interface 0. Since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. When using other output functions as well, disable output during SIN operation. SIN1 *1: FPT-120P-M05 *2: FPT-120P-M13 (Continued) 10 To Top / Lineup / Index MB90520 Series Pin no. LQFP-120*1 QFP-120*2 15 Pin name P46 Circuit type E Function This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a data output pin for extended I/O serial interface 0. This function becomes valid when serial data output from SOT1 is enabled. SOT1 16 P47 D This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial clock I/O pin for extended I/O serial interface 0. This function becomes valid when serial clock output from SCK1 is enabled. SCK1 35 P50 SIN2 D This is a general-purpose I/O port. This is a data input pin for extended I/O serial interface 1. Since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. This port can be used as count A input for 8/16-bit up/down counter/timer 1. AIN1 36 P51 SOT2 BIN1 37 P52 SCK2 D D This is a general-purpose I/O port. This function becomes valid when serial data output from SOT2 is enabled. This port can be used as count B input for 8/16-bit up/down counter/timer 1. This is a general-purpose I/O port. This is a serial clock I/O pin for extended I/O serial interface 1. This function becomes valid when serial clock output from serial SCK2 is enabled. This port can be used as control clock Z input for 8/16-bit up/down counter/timer 1. ZIN1 40, 41 P53, P54 DA0, DA1 46 to 53 P60 to P67 K I This is a general-purpose I/O port. These are analog signal output pins for 8-bit D/A converter ch.0 and ch.1. This is a general-purpose I/O port. The input function become valid when the analog input enable register (ADER) is set to select a port. These are analog input pins of the 8/10-bit A/D converter. This function is valid when the analog input enable register (ADER) is enabled. AN0 to AN7 *1: FPT-120P-M05 *2: FPT-120P-M13 (Continued) 11 To Top / Lineup / Index MB90520 Series Pin no. LQFP-120*1 QFP-120*2 55, 57 Pin name P70, P72 TI0, TI1 Circuit type E Function This is a general-purpose I/O port. These are event input pins for 16-bit re-load timers 0 and 1. Since this input is used as required for 16-bit re-load timers 0 and 1 operation, output by other functions must be suspended except for intentional operation. These are event output pins for output compare 1 (OCU) ch.4 and ch.6. This function is valid when output for each channel is enabled. OUT4, OUT6 56, 58 P71, P73 TO0, TO1 OUT5, OUT7 59 to 62 P74 to P77 L E This is a general-purpose I/O port. This function is valid with TO0 and TO1 output disabled. These are output pins for 16-bit re-load timers 0 and 1. This function is valid with TO0 and TO1 output is enabled. These are event output pins for output compare 1 (OCU) ch.5 and ch.7. This function is valid when output for each channel is enabled. This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are common pins for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. COM to COM3 64 to 71 P80 to P87 L This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are segment outputs for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. SEG16 to SEG23 72, 75 to 81 P90, P91 to P97 M This is a general-purpose I/O port. The maximum IOL can be 10mA. This function is valid with port output specified for the LCD controller/driver control register. These are ports for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. SEG24, SEG25 to SEG31 17 to 24 25 to 32 SEG00 to SEG07 F L These are pins dedicated to LCD segments 00 to 07 for the LCD controller/driver. This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are pins for LCD segments 08 to 15 for the LCD controller/ driver. Units of four ports or segments can be selected by the internal register in the LCD controller. PA0 to PA7 SEG08 to SEG15 *1: FPT-120P-M05 *2: FPT-120P-M13 12 (Continued) To Top / Lineup / Index MB90520 Series (Continued) Pin no. LQFP-120*1 QFP-120*2 34 C Pin name Circuit type G Function This is a capacitance pin for power supply stabilization. Connect an external ceramic capacitor rated at about 0.1 F. This capacitor is not, however, required for the M90F523 (flash product). This is a pin for the reference power supply for the LCD controller/ driver. This is power supply (5.0 V) input pin to the digital circuit. 82 to 85 8, 54, 94 33, 63, 91 119 42 V0 to V3 VCC N Power supply Power supply VSS This provides the GND level (0.0 V) input pin for the digital circuit. AVCC H This is power supply to the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVCC applied to VCC. This is a reference voltage input to the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVRH applied to AVCC. This is a reference voltage input to the analog circuit. This is a GND level of the analog circuit. This is the Vref input pin for the D/A converter. The voltage to be applied must not exceed VCC. This is the GND level pin for the D/A converter. The potential must be the same as VSS. 43 AVRH J 44 45 38 39 AVRL AVSS DVCC DVSS H H H H *1: FPT-120P-M05 *2: FPT-120P-M13 13 To Top / Lineup / Index MB90520 Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks * High-speed oscillation feedback resistor approx. 1M X0 Standby control signal B X1A * Low-speed oscillation feedback resistor approx. 1M X0A Standby control signal C R Hysteresis input * Hysteresis input rated at about 50 k D Selecting signal whether with a input pull-up resistor or without it * Hysteresis input can be set the input pullup resistor CMOS level output * Rated at about 50 k * Provided with a standby control function for input interruption R IOL = 4 mA Hysteresis input Standby control for input interruption (Continued) 14 To Top / Lineup / Index MB90520 Series Type E Circuit VCC Remarks * CMOS hysteresis input/output * CMOS level output * Provided with a standby control function for input interruption R Hysteresis input IOL = 4 mA Standby control for input interruption F R * Pins dedicated to segment output G * C pin output (Pin for capacitor connection) N.C. pin for the MB90F523 H * Analog power input protector AVP I VCC R Hysteresis input Standby control for input interruption IOL = 4 mA DAO * CMOS hysteresis input/output * Pin for analog output/CMOS output (During analog output, CMOS output is not produced.) (Analog output has priority over CMOS output: DAE = 1) * Provided with a standby control function for input interruption (Continued) 15 To Top / Lineup / Index MB90520 Series Type J Circuit Remarks * Input pin for ref+ power for the A/D converter Provided with a power protection ANE AVR ANE K * Hysteresis input/analog input * CMOS output * Provided with a standby control for input interruption R Hysteresis input Standby control for input interruption IOL = 4 mA Analog input L * Hysteresis input/output * Segment input * Standby control to cut off the input is available in segment input operation R Hysteresis input R SEG IOL = 4 mA M * Hysteresis input * N-ch open-drain output (High current for LCD drive) * Standby control to cut off the input is available in segment input operation R Hysteresis input IOL = 10 mA N R * Reference power supply pin for the LCD controller IOL = 10 mA 16 To Top / Lineup / Index MB90520 Series s HANDLING DEVICES 1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up). In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC) and analog input voltages not exceed the digital voltage (VCC). And also make sure the voltage applied to the LCD power supply pin (V3 to V0) doesn't exceed the power supply voltage (VCC). 2. Connection of Unused Pins Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up or a pull-down resistor. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock X0 Open X1 MB90520 series 4. Power Supply Pins In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. 5. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 17 To Top / Lineup / Index MB90520 Series 6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that AVRH and DVCC not exceed AVCC (turning on/off the analog and digital supplies simultaneously is acceptable). 7. Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL = VSS. 8. N.C. Pin The N.C. (internally connected) pin must be opened for use. 9. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more s (0.2 V to 2.7 V). 10. Use of SEG/COM Pins for the LCD Controller/Driver as Ports In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used general-purpose ports. The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type. 11. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. 12. Interrupt Recovery from the Standby State "H" level request must be an input request when using an external interrupt to recover from the standby state. In this case "L" level request may occur malfunction. 18 To Top / Lineup / Index MB90520 Series s BLOCK DIAGRAM F2MC-16LX CPU X0, X1 X0A, X1A RST HST P07 P00/INT0 to P06/INT6 7 Main clock Sub clock Clock control block*1 (including timebase timer) Port 0*2 7 DTP/ external interrupt circuit Port 8*5, 9*5, A*5 24 LCD controller/ driver 4 Port 7*4 16-bit re-load timer 0 16-bit re-load timer 1 16-bit I/O timer 2 Output 4 compare (OCU) 16-bit free-run timer 2 Input capture 1 (ICU) 8 8 8 8 4 4 P80/SEG16 to P87/SEG23 P90/SEG24 to P97/SEG31 PA0/SEG08 to PA7/SEG15 SEG00 to SEG07 V0 to V3 P74/COM0 to P77/COM3 P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7 Port 2*4 P24/AIN0 P25/BIN0 P26/ZIN0/INT7 3 8/16-bit up/down counter/timer 0, 1 16-bit I/O timer 1 2 Intrnal data bus P20/IC00 P21/IC01 2 Input capture 0 (ICU) 16-bit free-run timer 1 P22/IC10 P23/IC11 Port 2*4 Port 6*4 8 P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P31/CKOT P30 P36/PG00 P37/PG01 P40/PG10 P41/PG11 P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 4 compare 0 (OCU) Clock output Output 8 P60/AN0 to P67/AN7 AVCC AVSS AVRH AVRL P27/ADTG 8/10-bit A/D converter Port 3*4 2 2 8/16-bit PPG timer 0, 1 Port 2*4 Interrupt controller UART (SCI) Port 5*5 P50/SIN2/AIN1 P51/SOT2/BIN1 P52/SCK2/ZIN1 2 8-bit D/A converter x 2 ch. RAM ROM P53/DA0 P54/DA1 DVCC DVSS SIO ch.0 SIO ch.1 Port 4*2 Port 1*2 P10/WI0 to P17/WI7 8 8 Wake-up interrupt Other pins MD0 to MD2, C, VCC, VSS Notes: One 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported. *1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller. *2: A register for setting a pull-up resistor is supported. *3: This is a high-current port for LCD drive. *4: A register for setting a pull-up resistor is supported. A signal in the CMOS level is input and output. *5: Also used for LCD output. With this port used as is, N-ch open-drain output develops. A register for setting a pull-up resistor. 19 To Top / Lineup / Index MB90520 Series s MEMORY MAP Single chip mode A mirroring function is supported. FFFFFFH ROM area Address #1 FE0000H 010000H ROM area (image of bank FF) Address #2 004000H 002000H Address #3 RAM Register 000100H 0000C0H 000000H Peripheral Part number MB90522 MB90523 MB90F523 Address #1* FF0000H FE0000H FE0000H Address #2 * 004000H 004000H 004000H Address #3 * 001100H 001100H 001100H : Internal access memory : Access prohibited *: Addresses #1, #2 and #3 are unique to the product type. Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH 20 To Top / Lineup / Index MB90520 Series s F2MC-16LX CPU PROGRAMMING MODEL * Dedicated registers AH AL : Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer for containing a user stack address. : System stack pointer (SSP) The 16-bit pointer for displaying the status of the system stack address. : Processor status (PS) The 16-bit register for displaying the system status. : Program counter (PC) The 16-bit register for displaying storing location of the current instruction code. DPR : Direct page register (DPR) The 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register for displaying the program space. : Data bank register (DTB) The 8-bit register for displaying the data space. : User stack bank register (USB) The 8-bit register for displaying the user stack space. : System stack bank register (SSB) The 8-bit register for displaying the system stack space. : Additional data bank register (ADB) The 8-bit register for displaying the additional data space. USP SSP PS PC PCB DTB USB SSB ADB 8-bit 16-bit 32-bit 21 To Top / Lineup / Index MB90520 Series * General-purpose registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180H + (RP x 10H ) RW0 16-bit * Processor status (PS) ILM RP CCR bit 5 bit 4 S 1 T X bit 3 bit 2 N X Z X bit 1 V X bit 0 C X bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS Initial value -- : Unused X : Indeterminate ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 -- -- I 0 22 To Top / Lineup / Index MB90520 Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH EICR OCP5 OCU compare register ch.5 R/W (Disabled) Wake-up interrupt enable register W Wake-up interrupt Abbreviated register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA LCDCMR PDRC OCP4 Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port 7/COM pin selection register Port C data register OCU compare register ch.4 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 7, LCD controller/driver Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - - - XXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ----0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB Port C 16-bit I/O timer (output compare 1 (OCU) section) EIFR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER Wake-up interrupt flag register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog input enable register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Wake-up interrupt -------0B 00000000B 00000000B 00000000B 00000000B 00000000B ---00000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B XXXXXXXXB XXXXXXXXB Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/Dconverter 16-bit I/O timer (output compare 1 (OCU) section) 00000000B (Continued) 23 To Top / Lineup / Index MB90520 Series Address 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH Abbreviated register name SMR SCR SIDR/ SODR SSR SMCSL0 SMCSH0 SDR0 CDCR SMCSL1 SMCSH1 SDR1 Register name Serial mode register Serial control register Serial input data register/ serial output data register Serial status register Serial mode control lower status register 0 Serial mode control upper status register 0 Serial data register 0 Communications prescaler control register Serial mode control lower status register 1 Serial mode control upper status register 1 Serial data register 1 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) Resource name Initial value 00000000B UART (SCI) 00000100B XXXXXXXXB 00001-00B ----0000B Extended I/O serial interface 0 00000010B XXXXXXXXB Communications prescaler control register 0---1111B ----0000B Extended I/O serial interface 1 00000010B XXXXXXXXB 0000--00B OCS45 OCS67 ENIR EIRR ELVR OCU control status register ch.45 OCU control status register ch.67 DTP/interrupt enable register DTP/interrupt factor register Request level setting register R/W R/W R/W R/W R/W 16-bit I/O timer (output compare 1 (OCU) section) ----0000B 0000--00B ----0000B 00000000B XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB 00000000B DTP/external interrupt circuit 16-bit I/O timer OCP6 ADCS1 ADCS2 ADCR1 ADCR2 DADR0 DADR1 DACR0 DACR1 OCU compare register ch.6 A/D control status register lower digits A/D control status register upper digits A/D data register lower digits A/D data register upper digits D/A converter data register ch.0 D/A converter data register ch.1 D/A control register 0 D/A control register 1 R/W R/W R/W R R/W R/W R/W R/W R/W 8/10-bit D/A converter 8/10-bit A/D converter (output compare 1 (OCU) section) 00000000B XXXXXXXXB 0 0 0 0 1 - XXB XXXXXXXXB XXXXXXXXB -------0B -------0B (Continued) 24 To Top / Lineup / Index MB90520 Series Address 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H Abbreviated register name CLKR Register name Clock output enable register Read/ write R/W (Disabled) Resource name Clock monitor function Initial value ----0000B PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGOE0/ PPGOE1 PPG0 re-load register L PPG0 re-load register H PPG1 re-load register L PPG1 re-load register H PPG0 operating mode control register PPG1 operating mode control register PPG0 and 1 output control registers R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG timer 0, 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0-000--1B 0X000001B 00000000B (Disabled) TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 IPCP0 IPCP1 ICS01 Timer control status register ch.0 16-bit timer register ch.0/ 16-bit re-load register ch.0 Timer control status register ch.1 16-bit timer register ch.1/ 16-bit re-load register ch.1 ICU data register ch.0 ICU data register ch.1 ICU control status register R/W 16-bit re-load timer 0 R/W R/W 16-bit re-load timer 1 R/W R 16-bit I/O timer R R/W (Disabled) TCDT1 TCCS1 Free-run timer data register 1 Free-run timer control status register 1 (input compare 0, 1 (ICU) section) 00000000B ----0000B XXXXXXXXB XXXXXXXXB 00000000B ----0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B R/W R/W 16-bit I/O timer (16-bit free-run timer 1 section) (Disabled) (Continued) 25 To Top / Lineup / Index MB90520 Series Address 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H to 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H Abbreviated register name OCP0 OCP1 OCP2 OCP3 OCS01 OCS23 TCDT2 TCCS2 LCR0 LCR1 OCP7 Register name OCU compare register ch.0 OCU compare register ch.1 OCU compare register ch.2 OCU compare register ch.3 OCU control status register ch.01 OCU control status register ch.23 Free-run timer data register 2 Free-run timer control status register 2 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit I/O timer (output compare 0 (OCU) section) XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000--00B ---00000B 0000--00B ---00000B 00000000B 00000000B 00000000B 00010000B 00000000B XXXXXXXXB XXXXXXXXB 16-bit I/O timer (16-bit free-run timer 2 section) (Disabled) LCDC control registers 0 and 1 LCD controller/ driver 16-bit I/O timer (output compare 1 (OCU) section) OCU compare register ch.7 ROMM ROM mirroring function selection register RAM for LCD indication Up/down count register 0 Up/down count register 1 Re-load compare register 0 Re-load compare register 1 Counter status register 0 W ROM mirroring function selection module LCD controller/ driver -------1B VRAM UDCR0 UDCR1 RCR0 RCR1 CSR0 CCRL0 CCRH0 CSR1 R/W R R W W R/W (Reserved area)*3 XXXXXXXXB 00000000B 8/16-bit up/down counter/timer 0, 1 00000000B 00000000B 00000000B 00000000B -0000000B 00000000B 00000000B Counter control register 0 Counter status register 1 R/W R/W 8/16-bit up/down counter/timer 0, 1 (Continued) 26 To Top / Lineup / Index MB90520 Series Address 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH to 00009DH 00009EH Abbreviated register name CCRL1 CCRH1 RDR0 RDR1 RDR4 Register name Read/ write (Reserved area)*3 Resource name Initial value Counter control register 1 Port 0 input pull-up resistor setup register Port 1 input pull-up resistor setup register Port 4 input pull-up resistor setup register R/W R/W R/W R/W 8/16-bit up/down counter/timer 0, 1 Port 0 Port 1 Port 4 -0000000B -0000000B 00000000B 00000000B 00000000B (Area used by the system)*3 Program address detection control status register Delayed interrupt factor generation/ cancellation register Low-power consumption mode control register Clock select register Address match detection function Delayed interrupt generation module Low-power consumption (stand-by) mode PACSR R/W 00000000B 00009FH DIRR R/W -------0B 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH to 0000ADH 0000AEH 0000AFH LPMCR CKSCR R/W! R/W 00011000B 11111100B (Disabled) WDTC TBTC WTC Watchdog timer control register Timebase timer control register Clock timer control register R/W R/W R/W (Disabled) FMCS Flash control register R/W (Disabled) Flash interface 1--00100B Watchdog timer Timebase timer Clock timer XXXXXXXX B 1--00100B 1X000000B (Continued) 27 To Top / Lineup / Index MB90520 Series (Continued) Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH 000100H to 00####H 00####H to 001FEFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 001FF6H to 001FFFH Descriptions for read/write R/W: Readable and writable R: Read only W: Write only PADR1 PADR0 Abbreviated register name ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Register name Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (External area)*1 Interrupt controller Resource name Initial value 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (RAM area)*2 (Reserved area)*3 Program address detection register 0 Program address detection register 1 Program address detection register 2 Program address detection register 3 Program address detection register 4 Program address detection register 5 R/W R/W R/W R/W R/W R/W Program patch processing XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area)*3 28 To Top / Lineup / Index MB90520 Series Descriptions for initial value 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is indeterminate. - : This bit is not used. The initial value is indeterminate. *1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this area is handled as that to external I/O area. *2: For details of the RAM area, see the memory map. *3: The reserved area is basically disabled because it is used in the system. *4: Area used by the system is the area set by the resistor for evaluating tool. Notes: * For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. * The addresses following 0000FFH are reserved. No external bus access signal is generated. * Boundary ####H between the RAM area and the reserved area varies with the product model. * Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU) 0 and 1. 29 To Top / Lineup / Index MB90520 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt source Reset INT9 instruction Exception 8/10-bit A/D converter Timebase timer DTP0/DTP1 (external interrupt 0/ external interrupt 1) 16-bit free-run timer 1 overflow Extended I/O serial interface 0 Wake-up interrupt Extended I/O serial interface 1 DTP2/DTP3 (external interrupt 2/ external interrupt 3) 8/16-bit PPG timer 0 counter borrow DTP4/DTP5 (external interrupt 4/ external interrupt 5) 8/16-bit up/down counter/timer 0 compare match 8/16-bit up/down counter/timer 0 overflow/inversion 8/16-bit PPG timer 1 counter borrow DTP6/DTP7 (external interrupt 6/ external interrupt 7) Output compare 1 (OCU) ch.4/ch.5 match Clock prescaler Output compare 1 (OCU) ch.6/ch.7 match 16-bit free-run timer 2 overflow 8/16-bit up/down counter/timer 1 compare match 8/16-bit up/down counter/timer 1 overflow/inversion Input capture 0 (ICU) include Input capture 1 (ICU) include x x x x x x x EI2OS support x x x Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H ICR03 FFFFB4H FFFFB0H ICR04 FFFFACH FFFFA0H ICR05 FFFFA4H FFFFA0H ICR06 FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H FFFF7CH ICR10 ICR10 0000BAH 0000BAH Low 0000B9H ICR08 0000B8H 0000B6H 0000B5H 0000B4H 0000B3H ICR02 0000B2H ICR01 0000B1H Interrupt control register ICR -- -- -- ICR00 Address -- -- -- 0000B0H Priority High ICR07 0000B7H (Continued) 30 To Top / Lineup / Index MB90520 Series (Continued) Interrupt source Output compare 0 (OCU) ch.0 match Output compare 0 (OCU) ch.1 match Output compare 0 (OCU) ch.2 match Output compare 0 (OCU) ch.3 match UART (SCI) reception complete 16-bit re-load timer 0 UART (SCI) transmission complete 16-bit re-load timer 1 Reserved Delayed interrupt generation module : Can be used x : Can not be used : Can be used. With EI2OS stop function. x x x EI2OS support Interrupt vector Number # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFF78H ICR11 FFFF74H FFFF70H ICR12 FFFF6CH FFFF68H ICR13 FFFF64H FFFF60H ICR14 FFFF5CH FFFF58H FFFF54H ICR15 0000BFH Low 0000BEH 0000BDH 0000BCH 0000BBH Interrupt control register ICR Address Priority High 31 To Top / Lineup / Index MB90520 Series s PERIPHERALS 1. I/O Port (1) Input/Output Port Port 0 through 8, A are general-purpose I/O ports having a combined function as a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output, however, values of bits configured by the DDR register as inputs are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when configuring the bit used as input as outputs. * Operation as input port The pin is configured as an input by setting the corresponding bit of the DDR register to "0". When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1"). 32 To Top / Lineup / Index MB90520 Series (2) Register Configuration * Port 0 data register (PDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000000H (PDR1) P07 R/W bit 6 P06 R/W bit 11 P13 R/W bit 5 P05 R/W bit 10 P12 R/W bit 4 P04 R/W bit 9 P11 R/W bit 3 P03 R/W bit 2 P02 R/W bit 1 P01 R/W bit 0 P00 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B * Port 1 data register (PDR1) Address bit 15 000001H P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P10 R/W (PDR0) * Port 2 data register (PDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000002H (PDR3) P27 R/W bit 6 P26 R/W bit 5 P25 R/W bit 4 P24 R/W bit 3 P23 R/W bit 2 P22 R/W bit 1 P21 R/W bit 0 P20 R/W Initial value XXXXXXXX B * Port 3 data register (PDR3) Address bit 15 000003H P37 R/W bit 14 P36 R/W bit 13 P35 R/W bit 12 P34 R/W bit 11 P33 R/W bit 10 P32 R/W bit 9 P31 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P30 R/W (PDR2) Initial value XXXXXXXX B * Port 4 data register (PDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000004H (PDR5) P47 R/W bit 6 P46 R/W bit 11 P53 R/W bit 5 P45 R/W bit 10 P52 R/W bit 4 P44 R/W bit 9 P51 R/W bit 3 P43 R/W bit 2 P42 R/W bit 1 P41 R/W bit 0 P40 R/W Initial value - - - XXXXX B Initial value XXXXXXXX B * Port 5 data register (PDR5) Address bit 15 000005H -- -- bit 14 -- -- bit 13 -- -- bit 12 P54 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P50 R/W (PDR4) * Port 6 data register (PDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000006H (PDR7) P67 R/W bit 6 P66 R/W bit 5 P65 R/W bit 4 P64 R/W bit 3 P63 R/W bit 2 P62 R/W bit 1 P61 R/W bit 0 P60 R/W Initial value XXXXXXXX B * Port 7 data register (PDR7) Address bit 15 000007H P77 R/W bit 14 P76 R/W bit 13 P75 R/W bit 12 P74 R/W bit 11 P73 R/W bit 10 P72 R/W bit 9 P71 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P70 R/W (PDR6) Initial value XXXXXXXX B * Port 8 data register (PDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000008H (PDR9) P87 R/W bit 6 P86 R/W bit 5 P85 R/W bit 4 P84 R/W bit 3 P83 R/W bit 2 P82 R/W bit 1 P81 R/W bit 0 P80 R/W Initial value XXXXXXXX B * Port 9 data register (PDR9) Address 000009H bit 15 P97 R/W bit 14 P96 R/W bit 13 P95 R/W bit 12 P94 R/W bit 11 P93 R/W bit 10 P92 R/W bit 9 P91 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P90 R/W (PDR8) Initial value XXXXXXXX B (Continued) 33 To Top / Lineup / Index MB90520 Series * Port A data register (PDRA) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000AH (LCDCMR) PA7 R/W bit 6 PA6 R/W bit 6 D06 R/W bit 11 D13 R/W bit 5 PA5 R/W bit 5 D05 R/W bit 10 D12 R/W bit 4 PA4 R/W bit 4 D04 R/W bit 9 D11 R/W bit 3 PA3 R/W bit 3 D03 R/W bit 2 PA2 R/W bit 2 D02 R/W bit 1 PA1 R/W bit 1 D01 R/W bit 0 PA0 R/W bit 0 D00 R/W Initial value 00000000 B Initial value 00000000 B Initial value XXXXXXXX B * Port 0 direction register (DDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000010H (DDR1) D07 R/W * Port 1 direction register (DDR1) Address 000011H bit 15 D17 R/W bit 14 D16 R/W bit 13 D15 R/W bit 12 D14 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D10 R/W (DDR0) * Port 2 direction register (DDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000012H (DDR3) D27 R/W bit 6 D26 R/W bit 11 D33 R/W bit 5 D25 R/W bit 10 D32 R/W bit 4 D24 R/W bit 9 D31 R/W bit 3 D23 R/W bit 2 D22 R/W bit 1 D21 R/W bit 0 D20 R/W Initial value 00000000 B Initial value 00000000 B * Port 3 direction register (DDR3) Address 000013H bit 15 D37 bit 14 D36 bit 13 D35 bit 12 D34 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D30 R/W (DDR2) * Port 4 direction register (DDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000014H (DDR5) D47 R/W bit 6 D46 R/W bit 11 D53 R/W bit 5 D45 R/W bit 10 D52 R/W bit 4 D44 R/W bit 9 D51 R/W bit 3 D43 R/W bit 2 D42 R/W bit 1 D41 R/W bit 0 D40 R/W Initial value - - - 00000 B Initial value 00000000 B * Port 5 direction register (DDR5) Address 000015H bit 15 -- R/W bit 14 -- R/W bit 13 -- R/W bit 12 D54 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D50 R/W (DDR4) * Port 6 direction register (DDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000016H (DDR7) D67 R/W bit 6 D66 R/W bit 11 D73 R/W bit 5 D65 R/W bit 10 D72 R/W bit 4 D64 R/W bit 9 D71 R/W bit 3 D63 R/W bit 2 D62 R/W bit 1 D61 R/W bit 0 D60 R/W Initial value 00000000 B Initial value 00000000 B * Port 7 direction register (DDR7) Address 000017H bit 15 D77 R/W bit 14 D76 R/W bit 13 D75 R/W bit 12 D74 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D70 R/W (DDR6) * Port 8 direction register (DDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000018H (DDR9) D87 R/W bit 6 D86 R/W bit 5 D85 R/W bit 4 D84 R/W bit 3 D83 R/W bit 2 D82 R/W bit 1 D81 R/W bit 0 D80 R/W Initial value 00000000 B (Continued) 34 To Top / Lineup / Index MB90520 Series (Continued) * Port 9 direction register (DDR9) Address bit 15 000019H D97 R/W bit 14 D96 R/W bit 13 D95 R/W bit 12 D94 R/W bit 11 D93 R/W bit 10 D92 R/W bit 9 D91 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D90 R/W (DDR8) Initial value 00000000 B * Port A direction register (DDRA) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001AH (ADER) DA7 R/W Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00008CH (RDR1) RD07 R/W Address 00008DH bit 15 RD17 R/W bit 14 RD16 R/W bit 13 RD15 R/W bit 12 RD14 R/W bit 6 DA6 R/W bit 5 DA5 R/W bit 4 DA4 R/W bit 3 DA3 R/W bit 2 DA2 R/W bit 1 DA1 R/W bit 0 DA0 R/W Initial value 00000000 B * Port 0 input pull-up resistor setup register (RDR0) bit 6 RD06 R/W bit 11 RD13 R/W bit 5 RD05 R/W bit 10 RD12 R/W bit 4 RD04 R/W bit 9 RD11 R/W bit 3 RD03 R/W bit 2 RD02 R/W bit 1 RD01 R/W bit 0 RD00 R/W Initial value 00000000 B Initial value 00000000 B * Port 1 input pull-up resistor setup register (RDR1) bit 8 bit 7 . . . . . . . . . . . . bit 0 RD10 R/W (RDR0) * Port 4 input pull-up resistor setup register (RDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00008EH (Disabled) RD47 R/W bit 6 RD46 R/W bit 11 bit 5 RD45 R/W bit 10 ADE2 R/W bit 4 RD44 R/W bit 9 ADE1 R/W bit 3 RD43 R/W bit 2 RD42 R/W bit 1 RD41 R/W bit 0 RD40 R/W Initial value 11111111 B Initial value 00000000 B * Analog input enable register (ADER) Address 00001BH bit 15 ADE7 R/W bit 14 ADE6 R/W bit 13 ADE5 R/W bit 12 bit 8 bit 7 . . . . . . . . . . . . bit 0 ADE0 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 (PDRA) (DDRA) ADE4 ADE3 R/W R/W * Port 7/COM pin selection register (LCDCMR) Address 00000BH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 bit 10 bit 9 Initial value - - - - 0000 B COM3 COM2 COM1 COM0 R/W R/W R/W R/W R/W : Readable and writable -- : Unused X : Indeterminate 35 To Top / Lineup / Index MB90520 Series (3) Block Diagram * Input/output port PDR (port data register) PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode N-ch Pin P-ch * Input pull-up resistor setup register (RDR) PDR (port data register) To resource input PDR read Output latch PDR write DDR (port direction register) Internal data bus Direction latch DDR write Standby control (SPL=1) N-ch P-ch Pull-up resistor About 5.0 k (5.0 V) P-ch Pin DDR read RDR (input pull-up resistor setup register) RDR latch RDR write RDR read Standby control: Stop, timebase timer mode and SPL=1 36 To Top / Lineup / Index MB90520 Series * Analog input enable register (ADER) ADER (analog input enable register) ADER read ADER latch ADER write PDR (port data register) Internal data bus RMW (read-modify-write type instruction) To analog input PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) P-ch Pin N-ch DDR read Standby control: Stop, timebase timer mode and SPL=1 37 To Top / Lineup / Index MB90520 Series 2. Timebase Timer The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) Register Configuration * Timebase timer control register (TBTC) bit 7 . . . . . . . . . . . .bit 0 (WDTC) Initial value 1 - - 00000 B Address 0000A9H bit 15 RESV -- bit 14 -- -- bit 13 -- -- bit 12 TBIE R/W bit 11 TBOF R/W bit 10 TBR R/W bit 9 TBC1 R/W bit 8 TBC0 R/W R/W: Readable and writable -- : Unused RESV: Reserved bit (2) Block Diagram To 8/16-bit PPG timer Timebase timer counter Divided-by-2 of HCLK x 21 x 2 2 x 2 3 To watchdog timer ... ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To oscillation stabilization time selector of clock control block Power-on reset Start stop mode CKSCR : MCS = 10*1 Counter clear circuit Interval timer selector Set TBOF Clear TBOF Timebase timer control register (TBTC) Timebase timer interrupt signal #12*2 RESV -- -- TBIE TBOF TBR TBC1 TBC0 OF: Overflow HCLK: Oscillation clock *1: Switch machine clock from oscillation clock to PLL clock *2: Interrupt number 38 To Top / Lineup / Index MB90520 Series 3. Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A8H (TBTC) bit 6 bit 5 bit 4 bit 3 SRST R bit 2 WTE W bit 1 WT1 W bit 0 WT0 W PONR STBR WRST ERST R R R R Initial value XXXXXXXX B R : Read only W: Write only X : Indeterminate (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 Watchdog timer 2 CLR and start Overflow CLR Watchdog timer reset generation circuit To internal reset generation circuit Start sleep mode Start hold status Start stop mode Counter clear control circuit Count clock selector CLR 2-bit counter Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 22 ... 4 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK: Oscillation clock 39 To Top / Lineup / Index MB90520 Series 4. 8/16-bit PPG Timer 0, 1 The 8/16-bit PPG timer is a 2-CH re-load timer module for outputting pulse having given frequencies/duty ratios. The two modules performs the following operation by combining functions. * 8-bit PPG output 2-CH independent operation mode This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond to outputs from PPG0 and PPG1 respectively. * 16-bit PPG timer output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer 0 and 1 operating as a 16-bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same output pulses from PPG0 and PPG1 pins. * 8 + 8-bit PPG timer output operation mode In this mode, PPG0 is operated as an 8-bit communications pre-scaler, in which an underflow output of PPG0 is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1 respectively. * PPG output operation A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an external add-on circuit. 40 To Top / Lineup / Index MB90520 Series (1) Register Configuration * PPG0 operating mode control register (PPGC0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000044H (PPGC1) PEN0 R/W bit 6 -- -- bit 5 PE00 R/W bit 4 PIE0 R/W bit 3 PUF0 R/W bit 2 -- -- bit 1 -- -- bit 0 RESV -- Initial value 0 - 000 - - 1 B * PPG1 operating mode control register (PPGC1) Address bit 15 000045H PEN1 R/W bit 14 -- -- bit 13 PE10 R/W bit 12 PIE1 R/W bit 11 PUF1 R/W bit 10 MD1 R/W bit 9 MD0 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 RESV R/W (PPGC0) Initial value 0X0 0 0 0 0 1 B * PPG0 output control register (PPGOE0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000046H (Disabled) bit 6 bit 5 PCS0 R/W bit 5 PCS0 R/W bit 4 bit 3 bit 2 bit 1 PE11 R/W bit 1 PE11 R/W bit 0 PE01 R/W bit 0 PE01 R/W Initial value 00000000 B Initial value 00000000 B PCS2 PCS1 R/W R/W bit 6 PCM2 PCM1 PCM0 R/W bit 4 R/W bit 3 R/W bit 2 * PPG1 output control register (PPGOE1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000046H (Disabled) PCS2 PCS1 R/W R/W PCM2 PCM1 PCM0 R/W R/W R/W * PPG0 re-load register H (PRLH0) Address bit 15 000041H R/W R/W R/W R/W R/W R/W R/W R/W bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL0) Initial value XXXXXXXX B * PPG1 re-load register H (PRLH1) Address 000043H R/W R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL1) Initial value XXXXXXXX B * PPG0 re-load register L (PRLL0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000040H (PRLH0) R/W R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B R/W R/W: Readable and writable -- : Unused X : Indeterminate RESV: Reserved bit R/W R/W R/W R/W R/W R/W R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B * PPG1 re-load register L (PRLL1) 000042H (PRLH1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 41 To Top / Lineup / Index MB90520 Series (2) Block Diagram * Block diagram of 8/16-bit PPG timer 0 Data bus for "H" digits Data bus for "L" digits PPG0 re-load register PRLH0 PRLL0 PEN0 -- PPG0 operating mode control register (PPGC0) PE00 PIE0 PUF0 -- -- RESV Temporary buffer (PRLBH0) R S 2 Q Interrupt request #19* Mode control signal Re-load selector L/H selector Count value Re-load Select signal Clear Pulse selector Underflow PPG1 underflow PPG0 underflow (to PPG1) Down counter (PCNT0) CLK Reverse PPG0 output latch PPG output control circuit Count clock selector Pin P36/PG00 Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) Pin P37/PG01 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPG0, 1 output control register (PPGOE) * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 42 To Top / Lineup / Index MB90520 Series * Block diagram of 8/16-bit PPG timer 1 Data bus for "H" digits Data bus for "L" digits PPG1 re-load register PRLH0 Operating mode control signal Temporary buffer (PRLBH1) PRLL0 PEN1 -- 2 PPG1 operating mode control register (PPGC1) PEI0 PIE1 PUF1 MD1 MD0 RESV R S Q Interrupt request #23* Re-load selector (L/H selector) Count value Re-load Select signal Clear Underflow Reverse PPG1 output latch Down counter (PCNT1) PPG1 underflow (to PPG0) CLK Pin P40/PG10 PPG output control circuit MD0 Pin PPG0 underflow Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) P41/PG11 Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPG0, 1 Output control register (PPGOE) * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 43 To Top / Lineup / Index MB90520 Series 5. 16-bit Re-load Timer 0, 1 (With an Event Count Function) The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. For this timer, an "underflow" is defined as the timing of transition from the counter value of "0000H" to "FFFFH". According to this definition, an underflow occurs after [re-load register setting value + 1] counts. In operaring the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent I/O service (EI2OS). The MB90520 series has 2 channels of 16-bit re-load timers. (1) Register Configuration * Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H) Address TMCSR0 : 000049H TMCSR1 : 00004DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 CSL1 R/W bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (TMCSR : L) Initial value - - - - 0000 B CSL0 MOD2 MOD1 R/W R/W R/W * Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L) bit 6 bit 5 Address bit 15 . . . . . . . . . . . . bit 8 bit 7 TMCSR0 : 000048H (TMCSR : H) MOD0 OUTE OUTL TMCSR1 : 00004CH R/W R/W R/W bit 4 RELD R/W bit 3 INTE R/W bit 2 UF R/W bit 1 CNTE R/W bit 0 TRG R/W Initial value 00000000 B * 16-bit timer register upper and lower digits ch.0, ch.1 (TMR0, TMR1) Address TMR0 : 00004AH 00004BH TMR1 : 00004EH 00004FH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R R R R R R R R R R R R R R R R Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B * 16-bit re-load register upper and lower digits ch.0, ch.1 (TMRL0, TMRL1) Address TMRL0 : 00004AH 00004BH TMRL1 : 00004EH 00004FH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W W W W W W W W W W W W W W W W Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B R/W : Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate 44 To Top / Lineup / Index MB90520 Series (2) Block Diagram Internal data bus TMRLR0*1 Prescaler 3 Valid clock decision circuit Wait signal Clear Internal clock Input control circuit External clock P70/TI0/OUT4*1 3 CLK Output control circuit Clock selecter Output generation circuit To UART*1 Pin Pin EN P71/TO0/OUT5*1 Reverse Select signal -- -- -- -- CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD INTE UF CNTE TRG Clear EI2CS Interrupt request signal #40*1, *2 <#38> Timer control status register (TMCSR0)*1 45 To Top / Lineup / Index MB90520 Series 6. 16-bit I/O Timer The 16-bit I/O timer module consists of two 16-bit free-run timer, two input capture circuits (ICU), and eight output comparators (OCU). This module allows two independent waveforms to be output on the basis of the 16-bit free-run timer. Input pulse width and external clock periods can, therefore, be measured. * Block diagram Internal data bus Input capture 0, 1 (ICU) 16-bit Dedicated Dedicated Output compare 0, 1 free-run timer 1, 2 (OCU) bus bus 46 To Top / Lineup / Index MB90520 Series (1) 16-bit Free-run Timer 1, 2 The 16-bit free-run timer consists of a 16-bit up counter, a control register, and a communications prescaler register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and output compare (OCU). * A counter operation clock can be selected from four internal clocks (/4, /16, /32 and /64). * An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0 and 4. (Compare match requires mode setup.) * The counter value can be initialized to "0000H" by a reset, software clear or compare match with OCU compare register 0 and 4. * Register configuration * Free-run timer data register 1, 2 (TCDT1, TCDT2) Address TCDT1 : 000056H 000057H TCDT2 : 000066H 000067H bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 Initial value 00000000 B 00000000 B 00000000 B 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * Free-run timer control status register 1, 2 (TCCS1, TCCS2) Address TCCS1 : 000058H TCCS2 : 000068H bit 15. . . . . . . . . . . . .bit 8 bit 7 (Disabled) RESV R/W R/W: Readable and writable RESV: Reserved bit bit 6 IVF R/W bit 5 IVFE R/W bit 4 bit 3 bit 2 CLR R/W bit 1 CLK1 R/W bit 0 CLK0 R/W Initial value 00000000 B 00000000 B STOP MODE R/W R/W * Block diagram Count value output to ICO and OCU Free-run timer data register (TCDT1)*1 Communications pre-scaler register 2 Free-run timer control status register (TCCS1) *1 OCU compare register 0 match signal 16-bit free-run timer interrupt request #14*1, *2 <#28> *1: The timer has ch.1 and ch.2, and listed in the parenthesis < > are for ch.2. *2: Interrupt number : Machine clock frequency OF : Overflow Internal data bus 47 To Top / Lineup / Index MB90520 Series (2) Input Capture 0, 1 (ICU) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free-run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin. There are two sets (two channels) of the input capture external pins and ICU data registers, enabling measurements of maximum of four events. * The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measurements of maximum of four events. * A trigger edge direction can be selected from rising/falling/both edges. * The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free-run timer to the ICU data register (IPCP). * The input compare conforms to the extended intelligent I/O service (EI2OS). * The input capture ( ICU) function is suited for measurements of intervals (frequencies) and pulse-widths. * Register configuration * ICU data register ch.0 ch.1 (IPCP0, IPCP1) Address IPCP0 : 000051H IPCP1 : 000053H bit 15 CP15 R bit 14 CP14 R bit 13 CP13 R bit 12 CP12 R bit 11 CP11 R bit 10 CP10 R bit 9 CP09 R bit 8 bit 7 . . . . . . . . . . . . . bit 0 CP08 R (IPCP0, IPCP1) Initial value XXXXXXXXB Address IPCP0 : 000050H IPCP1 : 000052H bit 15. . . . . . . . . . . . bit 8 (IPCP0, IPCP1) bit 7 CP07 R bit 6 CP06 R bit 5 CP05 R bit 4 CP04 R bit 3 CP03 R bit 2 CP02 R bit 1 CP01 R bit 0 CP00 R Initial value XXXXXXXXB Note: This register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform is detected. (You can word-access this register, but you cannot program it.) * ICU cnotrol status register (ICS01) Address 000054H bit 15. . . . . . . . . . . . bit 8 (Disabled) bit 7 ICP1 R/W R/W : Readable and writable R : Read only X : Unused bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 EG11 R/W bit 2 EG10 R/W bit 1 bit 0 Initial value 00000000B EG01 EG00 R/W R/W 48 To Top / Lineup / Index MB90520 Series * Block diagram Internal data bus Latch signal P20/IC00 Pin P21/IC01 Pin P22/IC10 Pin P23/IC11 Pin 2 Data latch signal IPCP0H 2 IPCP1H IPCP1L 16 IPCP0L 16 16-bit free-run timer 1, 2 Edge detection circuit Output latch ICU data register (IPCP) ICU control status register (ICS01) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Interrupt request #31* Interrupt request #32* * : Interrupt number 49 To Top / Lineup / Index MB90520 Series (3) Output Compare 0, 1 (OCU) The output compare (OCU) is two sets of compare units consisting of a eight-channel OCU compare registers, a comparator and a control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run timer. The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit. * Register Configuration * OCU control status register ch.1, ch.23, ch.45, ch.67 (OCS01, OCS23, OCS45, OCS67) Address ch.01 : OCS01 : 0000063H ch.23 : OCS23 : 0000065H ch.45 : OCS45 : 000002DH ch.67 : OCS67 : 000002FH Address ch.01 : OCS01 : 000062H ch.23 : OCS23 : 000064H ch.45 : OCS45 : 00002CH ch.67 : OCS67 : 00002EH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 OTD0 R/W bit 3 -- -- bit 2 -- -- bit 1 CST1 R/W bit 0 CST0 R/W Initial value 0000 - - 00 B (OCS) Initial value - - - 00000 B CMOD OTE1 R/W bit 7 ICP1 R/W R/W bit 6 ICP0 R/W OTE0 OTD1 R/W bit 5 ICE1 R/W R/W bit 4 ICE0 R/W bit 15. . . . . . . . . . . . bit 8 (OCS) * OCU control status register ch.0 to ch.7 (OCS0 to OCS7) Address ch.0 : OCP0 : 00005BH ch.1 : OCP1 : 00005DH ch.2 : OCP2 : 00005FH ch.3 : OCP3 : 000061H ch.4 : OCP0 : 00000DH ch.5 : OCP1 : 00001DH ch.6 : OCP2 : 000035H ch.7 : OCP3 : 00006DH bit 15 C15 R/W bit 14 C14 R/W bit 13 C13 R/W bit 12 C12 R/W bit 11 C11 R/W bit 10 C10 R/W bit 9 C09 R/W bit 8 C08 R/W (OCP) Initial value XXXXXXXX B Address ch.0 : OCP0 : 00005AH ch.1 : OCP1 : 00005CH ch.2 : OCP2 : 00005EH ch.3 : OCP3 : 000060H ch.4 : OCP0 : 00000CH ch.5 : OCP1 : 00001CH ch.6 : OCP2 : 000034H ch.7 : OCP3 : 00006CH bit 7 (OCP) C07 R/W bit 6 C06 R/W bit 5 C05 R/W bit 4 C04 R/W bit 3 C03 R/W bit 2 C02 R/W bit 1 C01 R/W bit 0 C00 R/W Initial value XXXXXXXX B R/W : Readable and writable -- : Unused X : Indeterminate 50 To Top / Lineup / Index MB90520 Series * Block diagram * Output compare 0 (OCU) #36* #35* OCU control status register 23 (OCS23) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 2 2 16-bit free-run timer 1 -- -- CST1 CST0 Output compare interrupt request Compare control circuit 3 OCCP3 OCU compare register 3 Compare control circuit 2 Internal data bus OCCP2 OCU compare register 2 Output control circuit 2 Output control circuit 3 P35/OUT3 Pin P34/OUT2 Pin P33/OUT1 Pin P32/OUT0 Pin Compare control circuit 1 OCCP1 OCU compare register 1 Output control circuit 1 Compare control circuit 0 OCCP0 OCU compare register 0 2 2 Output control circuit 0 -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 #34* #33* OCU control status register 01 (OCS01) Output compare interrupt request * : Interrupt number 51 To Top / Lineup / Index MB90520 Series * Output compare 1 #27* OCU control status register 67 (OCS67) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 Output compare interrupt request -- -- CST1 CST0 2 2 16-bit free-run timer 2 Compare control circuit 7 OCCP3 OCU compare register 7 Internal data bus Compare control circuit 6 OCCP2 OCU compare register 6 Output control circuit 6 Output control circuit 7 P73/TO1/OUT7 Pin P72/TI1/OUT6 Pin P71/TO0/OUT5 Compare control circuit 5 OCCP1 OCU compare register 5 P70/TI0/OUT4 Compare control circuit 4 OCCP0 OCU compare register 4 2 2 Output control circuit 4 Output control circuit 5 Pin Pin -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 OCU control status register 45 (OCS45) #25* Output compare interrupt request * : Interrupt number 52 To Top / Lineup / Index MB90520 Series 7. 8/16-bit Up/Down Counter/Timer 0, 1 The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit re-load compare registers, and their controllers. (1) Register Configuration * Up/down count register 0 (UDCR0) Address 000080H bit 15 . . . . . . . . . . . . bit 8 bit 7 (UDCR1) D07 R bit 6 D06 R bit 11 D13 R bit 6 D06 W bit 11 D13 W bit 6 CITE R/W bit 6 bit 5 D05 R bit 10 D12 R bit 5 D05 W bit 10 D12 W bit 5 UDIE R/W bit 5 bit 4 D04 R bit 9 D11 R bit 4 D04 W bit 9 D11 W bit 4 CMPF R/W bit 4 bit 3 D03 R bit 8 D10 R bit 3 D03 W bit 8 D10 W bit 3 bit 2 bit 1 bit 0 UDF0 R bit 0 Initial value - 0000000 B Initial value 00000000 B bit 2 D02 W bit 1 D01 W bit 0 D00 W Initial value 00000000 B Initial value 00000000 B bit 2 D02 R bit 1 D01 R bit 0 D00 R Initial value 00000000 B Initial value 00000000 B * Up/down count register 1 (UDCR1) Address 000081H bit 15 D17 R Address 000082H bit 14 D16 R bit 13 D15 R bit 12 D14 R bit 7 . . . . . . . . . . . . . bit 0 (UDCR0) * Re-load compare register 0 (RCR0) bit 15 . . . . . . . . . . . . bit 8 bit 7 (RCR1) D07 W * Re-load compare register 1 (RCR1) Address 000083H bit 15 D17 W Address CSR0 : 000084H CSR1 : 000088H bit 14 D16 W bit 13 D15 W bit 12 D14 W bit 7 . . . . . . . . . . . . . bit 0 (RCR0) * Counter status register 0, 1 (CSR0, CSR1) bit 15 . . . . . . . . . . . . bit 8 bit 7 (Reserved area) CSTR R/W Address CSRL0 : 000086H CSRL1 : 00008AH bit 15 . . . . . . . . . . . . bit 8 bit 7 (CCRH0, CCRH1) OVFF UDFF UDF1 R/W bit 3 R/W bit 2 R bit 1 * Counter control register 0, 1 (CCRL0, CCRL1) -- -- * Counter control register 0 (CCRH0) Address 000087H bit 15 bit 14 bit 13 CFIE R/W bit 13 CFIE R/W bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (CCRL0) Initial value 00000000 B M16E CDCF R/W Address 00008BH bit 15 R/W bit 14 CDCF R/W CLKS CMS1 CMS0 CES1 CES0 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 (CCRL1) Initial value - 0000000 B CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W R/W R/W R/W R/W R/W R/W * Counter control register 1 (CCRH1) -- -- CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W : Readable and writable R : Read only W : Write only -- : Unused 53 To Top / Lineup / Index MB90520 Series (2) Block Diagram * Block diagram of 8/16-bit up/down counter/timer 0 Internal data bus RCR0 Re-load compare register 0 Re-load control circuit UDCR0 Up/down count register 0 Counter control register 0 (CCRL0) CARRY/ BORRW (to channel 1) -- CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Underflow Overflow P26/ZIN0/INT7 Pin Edge/level detection circuit Counter clear circuit Compare control circuit P24/AIN0 Pin Pin P25/BIN0 Prescaler Count clock Counter status register 0 (CSR0) UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Interrupt request #21* Interrupt request #22* M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 0 (CCRH0) M16E (to channel 1) * : Interrupt number : Machine clock frequency 54 To Top / Lineup / Index MB90520 Series * Block diagram of 8/16-bit up/down counter/timer 1 Internal data bus RCR1 Re-load compare register 1 Re-load control circuit Up/down count register 1 Counter control register 1 (CCRH1) UDCR1 -- CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Underflow Overflow P52/SCK2/ZIN1 Edge/level Pin detection circuit CARRY/BORRW (from channel 0) Counter clear circuit Compare control circuit P50/SIN2/AIN1 Pin Pin P51/SOT2/BIN1 M16E (from channel 1) Prescaler Count clock Counter status (CSR1) register 1 UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Interrupt request #29* Interrupt request #30* -- CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 1 (CCRH1) * : Interrupt number : Machine clock frequency 55 To Top / Lineup / Index MB90520 Series 8. Extended I/O Serial Interface 0, 1 The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. For data transfer, you can select LSB first/MSB first. (1) Register Configuration * Serial mode control upper status register 0, 1 (SMCSH0, SMCSH1) Address SMCSH0 : 000025H SMCSH1 : 000029H bit 15 bit 14 bit 13 bit 12 SIE R/W bit 11 SIR R/W bit 6 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (SMCSL) Initial value 00000010 B SMD2 SMD1 SMD0 R/W Address SMCSL0 : 000024H SMCSL1 : 000028H R/W R/W BUSY STOP STRT R bit 5 R/W bit 4 R/W bit 3 MODE R/W bit 3 D3 R/W bit 2 BDS R/W bit 2 D2 R/W bit 1 SOE R/W bit 1 D1 R/W bit 0 SCOE R/W bit 0 D0 R/W Initial value XXXXXXXX B Initial value - - - - 0000 B * Serial mode control lower status register 0, 1 (SMCSL0, SMCSL1) bit 15 . . . . . . . . . . . . bit 8 bit 7 (SMCSH) -- -- * Serial data register 0, 1 (SDR0, SDR1) Address SDR0 : 000026H SDR1 : 00002AH (CDCR, disabled) -- -- bit 6 D6 R/W -- -- bit 5 D5 R/W -- -- bit 4 D4 R/W bit 15 . . . . . . . . . . . . bit 8 bit 7 D7 R/W R/W : Readable and writable R : Read only -- : Unused X : Indeterminate 56 To Top / Lineup / Index MB90520 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Transfer direction selection Pin P45/SIN1 Pin P50/SIN2/AIN1 Pin P46/SOT1 Pin Pin P47/SCK1 Pin P52/SCK2/ZIN1 Internal clock Control circuit P51/SOT2/BIN1 Shift clock counter Serial data register (SDR) Read Write 3 0 SIR BUSY STOP STRT 2 1 SMD2 SMD1 SMD0 SIE -- -- -- -- MODE BDS SOE SCOE Serial mode control status register (SMCS) *: Interrupt number Interrupt request #15 (SMCS0)* #17 (SMCS1)* 57 To Top / Lineup / Index MB90520 Series 9. UART (SCI) UART (SCI) is general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: Embedded dedicated baud rate generator External clock input possible Internal clock (a clock supplied from 16-bit re-load timer can be used.) Internal machine clock Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps For 6 MHz, 8 MHz, 10 MHz, CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps 12 MHz and 16 MHz * Data length: 7 bit to 9 bit selective (without a parity bit) 6 bit to 8 bit selective (with a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) * Interrupt request: Receive interrupt (receive complete, receive error detection) Receive interrupt (transmit complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) } 58 To Top / Lineup / Index MB90520 Series (1) Register Configuration * Serial control register (SCR) Address 000021H bit 15 PEN R/W bit 14 P R/W bit 13 SBL R/W bit 12 CL R/W bit 7 MD1 R/W bit 11 A/D R/W bit 6 MD0 R/W bit 11 bit 10 REC W bit 5 CS2 R/W bit 10 -- -- bit 5 D5 R bit 5 D5 W bit 10 DIV2 R/W bit 9 RXE R/W bit 4 CS1 R/W bit 9 RIE R/W bit 4 D4 R bit 4 D4 W bit 9 DIV1 R/W bit 8 TXE R/W bit 3 CS0 R/W bit 8 TIE R/W bit 3 D3 R bit 3 D3 W bit 8 DIV0 R/W bit 2 D2 R bit 2 D2 W bit 1 D1 R bit 1 D1 W bit 0 D0 R bit 0 D0 W bit 2 RESV R/W bit 1 SCKE R/W bit 0 SOE R/W bit 7 . . . . . . . . . . . . . bit 0 (SMR) Initial value 00000100 B * Serial mode register (SMR) Address 000020H bit 15. . . . . . . . . . . . bit 8 (SCR) Initial value 00000000 B * Serial status register (SSR) Address 000023H bit 15 PE R bit 14 ORE R bit 13 FRE R bit 12 bit 7 . . . . . . . . . . . . . bit 0 (SIDR/SODR) RDRF TRDE R bit 7 D7 R R bit 6 D6 R bit 6 D6 W bit 11 DIV3 R/W Initial value 00001 - 00 B * Serial input data register (SIDR) Address 000022H bit 15. . . . . . . . . . . . bit 8 (SSR) Initial value XXXXXXXX B * Serial output data register (SODR) Address 000022H bit 15. . . . . . . . . . . . bit 8 (SSR) bit 7 D7 W Address 000027H bit 15 MD bit 14 -- bit 13 -- -- bit 12 -- -- Initial value XXXXXXXX B * Communications prescaler control register (CDCR) bit 7 . . . . . . . . . . . . . bit 0 (SDR0) Initial value 0 - - - 1111 B R/W -- R/W: Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate RESV : Reserved bit 59 To Top / Lineup / Index MB90520 Series (2) Block Diagram Control bus Receive interrupt signal #37* Transmit interrupt signal #39* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P43/SOT0 Dedicated baud rate generator 16-bit re-load timer 0 External clock Pin P42/SCK0 Start bit detection circuit Receive bit counter Receive parity counter Clock selector Transmit clock Receive clock Receive control circuit Pin P42/SIN0 Shift register for reception Reception complete Shift register for transmission SIDR0 Receive condition decision circuit SODR0 Start transmission To EI2OS reception error generation signal (to CPU) Internal data bus SMR0 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0 register PEN P SBL CL A/D REC RXE TXE SSR0 register PE ORE FRE RDRF TDRE RIE TIE * : Interrupt number 60 To Top / Lineup / Index MB90520 Series 10. DTP/External Interrupt Circuit DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit* for transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing. As request levels, two types of "H" and "L" can be selected for the intelligent I/O service. Rising and falling edges as well as "H" and "L" can be selected for an external interrupt request. * : The external peripheral circuit is connected outside the MB90520 series device. (1) Register Configuration * DTP/interrupt factor register (EIRR) Address bit 15 000031H ER7 R/W bit 14 ER6 R/W bit 13 ER5 R/W bit 12 ER4 R/W bit 11 ER3 R/W bit 10 ER2 R/W bit 9 ER1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 ER0 R/W (ENIR) Initial value XXXXXXXX B * DTP/interrupt enable register (ENIR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000030H (EIRR) EN7 R/W bit 6 EN6 R/W bit 5 EN5 R/W bit 4 EN4 R/W bit 3 EN3 R/W bit 2 EN2 R/W bit 1 EN1 R/W bit 0 EN0 R/W Initial value 00000000 B * Request level setting register (ELVR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 Low order address 000032H (ELVR upper) LB3 R/W Address bit 15 High order address 000033H LB7 R/W bit 14 LA7 R/W bit 13 LB6 R/W bit 12 LA6 R/W bit 6 LA3 R/W bit 11 LB5 R/W bit 5 LB2 R/W bit 10 LA5 R/W bit 4 LA2 R/W bit 9 LB4 R/W bit 3 LB1 R/W bit 2 LA1 R/W bit 1 LB0 R/W bit 0 LA0 R/W Initial value 00000000 B Initial value 00000000 B bit 8 bit 7 . . . . . . . . . . . . bit 0 LA4 R/W (ELVR lower) R/W: Readable and writable X : Indeterminate 61 62 Request level setting register (ELVR) LB7 2 2 2 2 2 2 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin Level edge selector 7 Level edge selector 5 Level edge selector 3 2 Level edge selector 1 2 (2) Block Diagram MB90520 Series P26/ZIN0/INT7 Pin Level edge selector 6 Level edge selector 4 Level edge selector 2 Level edge selector 0 P06/INT6 Pin P05/INT5 DTP/external intrrupt input detection circuit To Top / Lineup / Index *: Interrupt number Internal data bus ER7 ER6 ER5 ER4 ER3 ER2 ER1 #24* #20* #18* #13* EN7 EN6 EN5 EN4 EN3 EN2 EN1 P04/INT4 ER0 DTP/interrupt factor register (EIRR) Pin P03/INT3 Pin P02/INT2 Pin P01/INT1 Pin P00/INT0 EN0 DTP/interrupt enable register (ENIR) To Top / Lineup / Index MB90520 Series 11. Wake-up Interrupt Wake-up intrrupts transmits interrupt request ("L" level) generated by peripheral equipment located between external periphera devices and the F2MC-16LX CPU to the CPU and invokes interrupt processing. The interrupt does not conform to the exterded intelligent I/O service (EI2OS). (1) Register Configuration * Wake-up interrupt flag register (EIFR) Address 00000FH bit 15 -- -- Address 00001FH bit 15 EN7 W bit 14 -- -- bit 14 EN6 W bit 13 -- -- bit 13 EN5 W bit 12 -- -- bit 12 EN4 W bit 11 -- -- bit 11 EN3 W bit 10 -- -- bit 10 EN2 W bit 9 -- -- bit 9 EN1 W bit 8 bit 7 . . . . . . . . . . . . bit 0 WIF R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 EN0 W (Disabled) Initial value 00000000 B (Disabled) Initial value - - - - - - -0B * Wake-up interrupt enable register (EICR) R/W: Readable and writable W : Write only -- : Unused (2) Block Diagram Internal data bus Wake-up interrupt enable register (EICR) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Wake-up interrupt flag register (EIFR) -- -- -- -- -- -- -- WIF Interrupt request detection circuit P10/WI0 Pin P11/WI1 Pin Wake-up interrupt request #16* P12/WI2 Pin P13/WI3 Pin P14/WI4 P15/WI5 P16/WI6 P17/WI7 Pin Pin Pin Pin *: Interrupt number 63 To Top / Lineup / Index MB90520 Series 12. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Delayed interrupt factor generation/cancellation register (DIRR) Address 00009FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 R0 R/W (PACSR) Initial value - - - - - - -0B Note: Upon a reset, an interrupt is canceled. R/W: Readable and writable -- : Unused The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this register with "1" generates a delay interrupt request. Programming this register with "0" cancels a delay interrupt request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either "0" or "1". For future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) Block Diagram Internal data bus -- -- -- -- -- -- -- R0 S factor R latch Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt number Interrupt request signal #42* 64 To Top / Lineup / Index MB90520 Series 13. 8/10-bit A/D Converter The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features. * Minimum conversion time: 16.3 s (at machine clock of 16 MHz, including sampling time) * Minimum sampling period: 4 s/8 s/16 s/256 s (at machine clock of 16 MHz) * Compare time: 99/176 machine cycles per channel. (99 machine cycles are used for a machine clock below 10 MHz.) * Conversion method: RC successive approximation method with a sample and hold circuit. * 8/10-bit resolution * Analog input pins: Selectable from eight channels by software Single conversion mode: Selects and converts one channel. Scan conversion mode: Converts two or more successive channels. Up to eight channels can be programmed. Continuous conversion mode: Repeatedly converts specified channels. Stop conversion mode: Stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously.) * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling efficient continuous processing. * When interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. * Starting factors for conversion: Selected from software activation, and external trigger (falling edge). 65 To Top / Lineup / Index MB90520 Series (1) Register Configuration * A/D control status register upper digits (ADCS2) Address 000037H bit 15 BUSY R/W bit 14 INT R/W bit 13 INTE R/W bit 12 PAUS R/W bit 11 STS1 R/W bit 10 STS0 R/W bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (ADCS1) STRT RESV W R/W Initial value 00000000 B * A/D control status register lower digits (ADCS1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000036H (ADCS2) MD1 R/W bit 6 MD0 R/W bit 5 ANS2 R/W bit 4 ANS1 R/W bit 3 ANS0 R/W bit 2 ANE2 R/W bit 1 ANE1 R/W bit 0 ANE0 R/W Initial value 00000000 B * A/D data register upper digits (ADCR2) Address 000039H bit 15 RESV W bit 14 ST1 W bit 13 ST0 W bit 12 CT1 W bit 11 XCT0 W bit 10 -- -- bit 9 (D9) R bit 8 bit 7 . . . . . . . . . . . . bit 0 (D8) R (ADCR1) Initial value 0 0 0 0 1 - XX B * A/D data register lower digits (ADCR1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000038H (ADCR2) D7 R R/W: Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate RESV : Reserved bit bit 6 D6 R bit 5 D5 R bit 4 D4 R bit 3 D3 R bit 2 D2 R bit 1 D1 R bit 0 D0 R Initial value XXXXXXXX B 66 To Top / Lineup / Index MB90520 Series (2) Block Diagram A/D control status register (ADCS) Interrupt request #11* BUSY INT INTE PAUS STS1 STS0 STRT DA MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6 P27/ADTG P73/TO1/OUT7 2 Clock selector Decoder Comparator P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 Sample hold circuit Analog channel selector AVRH, AVRL AVCC AVSS 8-bit D/A converter Control circuit A/D data register SELB ST1 ST0 CT1 CT0 (ADCR) -- (D9) (D8) D7 D6 D5 D4 D3 D2 D1 D0 : Machine clock frequency TO : 16-bit PPG timer channel 1 output * : Interrupt number Internal data bus 67 To Top / Lineup / Index MB90520 Series 14. 8-bit D/A Converter The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two channels each of which can be controlled in terms of output by the D/A control register. (1) Register Configuration * D/A converter data register ch.0 (DADR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003AH (DADR1) DA07 R/W bit 6 DA06 R/W bit 5 DA05 R/W bit 4 DA04 R/W bit 3 DA03 R/W bit 2 DA02 R/W bit 1 DA01 R/W bit 0 DA00 R/W Initial value XXXXXXXX B * D/A converter data register ch.1 (DADR1) Address 00003BH bit 15 DA17 R/W bit 14 DA16 R/W bit 13 DA15 R/W bit 12 DA14 R/W bit 11 DA13 R/W bit 10 DA12 R/W bit 9 DA11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 DA10 R/W (DADR0) Initial value XXXXXXXX B * D/A control register 0 (DACR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003CH (DACR1) -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 -- -- bit 2 -- -- bit 1 -- -- bit 0 DAE0 R/W Initial value - - - - - - -0B * D/A control register 1 (DACR1) Address 00003DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 DAE1 R/W (DACR0) Initial value - - - - - - -0B R/W: Readable and writable -- : Unused X : Indeterminate 68 To Top / Lineup / Index MB90520 Series * Block Diagram Internal data bus D/A converter data register ch.1 (DADR1) DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 D/A converter data register ch.0 (DADR0) DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A converter 1 DVRH DA17 Pin 2R DA16 2R DA15 2R DA14 2R DA13 2R DA12 2R DA11 2R DA10 2R 2R DVSS Standby control R P54/DA1 D/A converter 0 DVRL DA07 Pin 2R DA06 2R DA05 2R DA04 2R DA03 2R DA02 2R DA01 2R DA00 2R R P53/DA0 R R R R R R R R R R R R 2R DVSS Standby control D/A control register 1 (DACR1) -- -- -- -- -- -- -- DAE1 D/A control register 0 (DACR0) -- -- -- -- -- -- -- DAE0 Internal data bus 69 To Top / Lineup / Index MB90520 Series 15. Clock Timer The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt. (1) Register Configuration * Clock timer control register (WTC) . . . . . . . . . . . . bit 8 bit 7 Address bit 15 0000AAH (Disabled) WDCS R/W R/W: Readable and writable R : Read only X : Indeterminate bit 6 SCE R bit 5 bit 4 bit 3 WTR R bit 2 bit 1 bit 0 Initial value 1X0 0 0 0 0 0 B WTIE WTOF R/W R/W WTC2 WTC1 WTC0 R/W R/W R/W (2) Block Diagram To watchdog timer Timer counter LCLK x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 OF OF OF OF OF OF OF Power-on reset Shift to a hardware standby Shift to stop mode Interval timer selector Counter clear circuit To sub-clock oscillation stabilization time controller Clock timer interrupt request #22* WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clock timer control register (WTC) * : Interrupt number OF : Overflow LCLK : Oscillation sub-clock frequency 70 To Top / Lineup / Index MB90520 Series 16.LCD Controller/Driver The LCD controller/driver, which contains a 16-byte display data memory, controls LCD indication using four common output pins and 32 segment output pins. It can select three types of duty output, and directly drive the LCD (liquid crystal display) panel. (1) Register Configuration * LCDC control register 0 (LCR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00006AH (LCR1) CSS R/W bit 6 LCEN R/W bit 5 VSEL R/W bit 4 BK R/W bit 3 MS1 R/W bit 2 MS0 R/W bit 1 FP1 R/W bit 0 FP0 R/W Initial value 00010000 B * LCDC control register 1 (LCR1) Address 00006BH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (LCR10) RESV SEG5 SEG4 RESV SEG3 R/W SEG2 SEG1 SEG0 R/W R/W R/W Initial value 00000000 B * Port 7/COM pin selection register (LCDCMR) Address 00000BH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PDRA) COM3 COM2 COM1 COM0 R/W R/W W R/W Initial value - - - - 0000 B R/W: Readable and writable -- : Unused X : Indeterminate RESV : Reserved bit 71 To Top / Lineup / Index MB90520 Series (2) Block Diagram Pin LCDC control register 0 (LCR0) CSS LCEN VSEL BK MS1 MS0 FP1 FP0 Pin Split resistor Pin Pin 2 Pin HCLK LCLK Prescaler Timing controller generator V0 V1 V2 V3 COM0 COM1 COM2 COM3 SEG00 SEG01 SEG02 Commen driver Internal data bus Pin Pin Pin AC Pin Indication RAM (16 bytes) 32 Pin 6 Segment driver Pin ......... Pin Pin Pin RESV SEG5 SEG4 RESV SEG3 SEG2 SEG1 SEG0 LCDC control register 1 (LCR1) Controller section P95/SEG29 P76/SEG30 P77/SEG31 HCLK : Oscillation frequency LCLK : Oscillation sub-clock frequency 72 ......... To Top / Lineup / Index MB90520 Series 17. Communications Prescaler Register This register controls machine clock division. Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O serial interface. The communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) Register Configuration * Communications prescaler control register (CDCR) Address 000027H bit 15 MD R/W bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 DIV3 R/W bit 10 DIV2 R/W bit 9 DIV1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 DIV0 R/W (SDR0) Initial value 0 - - - 1111 B R/W: Readable and writable -- : Unused 73 To Top / Lineup / Index MB90520 Series 18. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit and flag are prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1", the interrupt flag is set at "1" and the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. The interrupt flag is cleared to "0" by writing 0 by an instruction. (1) Register Configuration * Program address detection register 0 to 2 (PADR0) Address PADR0 (Low order address) : 001FF0H R/W Address PADR0 (Middle order address) : 001FF1H R/W Address PADR0 (High order address) : 001FF2H R/W Address PADR1 (Low order address) : 001FF3H R/W Address PADR1 (Middle order address) : 001FF4H R/W Address PADR1 (High order address) : 001FF5H R/W Address 00009EH bit 7 RESV -- R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 AD1D R/W R/W bit 1 AD0E R/W R/W bit 0 AD0D R/W Initial value 00000000 B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B * Program address detection register 3 to 5 (PADR1) * Program address detection control status register (PACSR) RESV RESV -- -- RESV AD1E -- R/W R/W: Readable and writable -- : Unused X : Indeterminate RESV : Reserved bit 74 To Top / Lineup / Index MB90520 Series (2) Block Diagram Compare Address latch Internal data bus Address detection register INT9 instruction Enable bit Detect bit Reset F2MC-16LX CPU core Set 75 To Top / Lineup / Index MB90520 Series 19. ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register Configuration * ROM mirroring function selection register (ROMM) Address 00006FH bit 15 -- -- W : Write only -- : Unused bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 MI W (Disabled) Initial value - - - - - - -1B Note: Do not access this register during operation at addresses 004000H to 00FFFFH. (2) Block Diagram ROM mirroring function selection register (ROMM) Internal data bus Address area Address FF bank 00 bank Data ROM 76 To Top / Lineup / Index MB90520 Series 20. Low-power Consumption (Stand-by) Mode The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation clock (HCLK). Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscillation clock (HCLK). The PLL multiplication circuits stops in the mainclock mode. * CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high-speed. * Hardware stand-by mode The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes, modes other than the PLL clock mode are power consumption modes. (1) Register Configuration * Clock select register (CKSCR) Address 0000A1H bit 15 SCM R bit 14 MCM R bit 13 WS1 R/W bit 12 WS0 R/W bit 11 SCS R/W bit 6 SLP W bit 10 MCS R/W bit 5 SPL R/W bit 9 CS1 R/W bit 4 RST W bit 8 bit 7 . . . . . . . . . . . . bit 0 CS0 R/W bit 3 TMD W bit 2 CG1 R/W bit 1 CG0 R/W bit 0 SSR R/W (LPMCR) Initial value 11111100 B * Low-power consumption mode control register (LPMCR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A0H (CKSCR) STP W R/W: Readable and writable R : Read only W : Write only Initial value 00011000 B 77 To Top / Lineup / Index MB90520 Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 SSR CPU intermittent operation cycle selector 2 Clock mode Sleep signal Stop signal CPU clock control circuit CPU operation clock Hardware standby Peripheral clock control circuit S R S R Q Q S R S R Q Q Machine clock Peripheral function operation clock Reset Interrupt Clock selector 2 Oscillation stabilization time selector 2 PLL multiplication circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) X0 X1 Pin Pin Clock oscillator Oscillation clock Dividedby-2 Main clock Dividedby-2048 Dividedby-4 Dividedby-4 Dividedby-8 Timebase timer To watchdog timer X0A Pin X1A Pin Oscillation sub-clock Sub-clock oscillator Dividedby-1024 Dividedby-8 Dividedby-2 Dividedby-2 Clock timer S : Set R : Reset Q : Output 78 To Top / Lineup / Index MB90520 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC Power supply voltage AVRH, AVRL DVCC Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total average output current Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5: VI VO IOL IOLAV IOLAV IOH IOHAV IOHAV PD TA Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 6.0 VCC + 6.0 15 4 100 50 -15 -4 -100 -50 300 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *1 *1 *1 *2 *2 *3 *4 Remarks "L" level total maximum output current IOL "H" level total maximum output current IOH AVCC, AVRH, AVRL, and DVCC shall never exceed VCC. AVRL shall never exceed AVRH. VI and VO shall never exceed VCC + 0.3 V. The maximum output current is a peak value for a corresponding pin. Average output current is an average current value observed for a 100 ms period for a corresponding pin. Total average current is an average current value observed for a 100 ms period for all corresponding pins. Note: Average output current = operating currnet x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 79 To Top / Lineup / Index MB90520 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage VCC VCC Smoothing capacitor Operating temperature CS TA Value Min. 3.0 4.5 3.0 0.1 -40 Max. 5.5 5.5 5.5 1.0 +85 Unit V V V F C Remarks Normal operation (MB90523) Normal operation (MB90F523) Guaranteed frequency = 10 MHz at 4.0 V to 4.5V Retains status at the time of operation stop * * : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C pin diagram C CS 80 To Top / Lineup / Index MB90520 Series 3. DC Characteristics (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. 0.7 VCC 0.8 VCC VCC = 3.0 V to 5.5 V VCC - 0.3 (MB90523) VCC = 4.0 V to 5.5 V VSS - 0.3 (MB90F523) Parameter Symbol VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage "H" level output voltage "L" level output voltage VILS VILM VOH Pin name CMOS input pin CMOS hysteresis input pin MD pin input CMOS input pin CMOS hysteresis input pin MD pin input Other than P90 and P97 All output pins -- -- -- -- -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 -- V V V V V V V VSS - 0.3 VSS - 0.3 VCC = 4.5 V IOH = -2.0 mA VCC = 4.5 V IOL = 2.0 mA VCC - 0.5 VOL -- -- 0.4 V Open-drain output Ileak leakage current Input leakage current Pull-up resistance Pull-down resistance IIL Output pin P90 to P97 Other than P90 and P97 P00 to P07, P10 to P17, P40 to P47, RST, MD0, MD1 MD0 to MD2 -- -- 0.1 5 A VCC = 5.5 V VSS < VI < VCC -5 -- 5 A RUP -- 15 30 100 k RDOWN -- 15 30 100 k (Continued) 81 To Top / Lineup / Index MB90520 Series (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. Internal operation at 16 MHz VCC at 5.0 V Normal operation Internal operation at 16 MHz VCC at 5.0 V A/D converter operation Internal operation at 16 MHz VCC at 5.0 V D/A converter operation When data written in flash mode is erased Internal operation at 16 MHz VCC at 5.0 V In sleep mode Internal operation at 8 kHz VCC at 5.0 V TA = +25C Subsystem operatin Internal operation at 8 kHz VCC at 5.0 V TA = +25C In subsleep mode Internal operation at 8 kHz VCC at 5.0 V TA = +25C In clock mode TA = +25C In stop mode TA = +25C (max.) In stop mode -- -- -- -- -- -- -- 30 85 35 90 40 95 40 130 45 140 50 145 mA MB90523 mA MB90F523 mA MB90523 mA MB90F523 mA MB90523 mA MB90F523 Parameter Symbol ICC ICC ICC ICC ICC ICC VCC VCC VCC VCC VCC VCC Pin name ICC ICCS Power supply current* ICCS ICCL VCC VCC VCC VCC -- -- -- -- 95 7 5 0.1 140 12 30 1.0 mA MB90F523 mA MB90523 mA MB90F523 mA MB90523 ICCL VCC -- 4 7 mA MB90F523 ICCLS ICCLS ICCT ICCT ICCH ICCH ICCH Input CIN capacitance VCC VCC VCC VCC VCC VCC VCC Other than AVCC, AVSS, VCC, VSS -- -- -- -- -- -- -- -- 30 0.1 15 30 5 0.1 -- 10 50 1 30 50 20 10 200 80 mA MB90523 mA MB90F523 A A A A A pF MB90523 MB90F523 MB90523 MB90F523 MB90F523 (Continued) 82 To Top / Lineup / Index MB90520 Series (Continued) Parameter Symbol LCD split resistor Pin name V0 to V1, V1 to V2, V2 to V3 COM0 to COM3 V1 to V3 = 5.0 V SEG00 to SEG31 (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. -- 50 100 200 k RLCD Output impedance RVCOM for COM0 to COM3 Output impedance RVSEG for SEG00 to SEG31 LCDC leak ILCKC current -- -- 2.5 k -- -- 15 k V0 to V3, COM1 to COM3, SEG00 to SEG31 -- -- -- 5 A * : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice.The power supply current is measured with an external clock. 83 To Top / Lineup / Index MB90520 Series 4. AC Characteristics (1) Reset, Hardware Standby Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRSTL tHSTL RST HST -- 4 tCP* 4 tCP* -- -- ns ns Parameter Reset input time Hardware standby input time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * Measurement conditions for AC ratings Pin CL CL is a load capacitance connected to a pin under test. Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must be connected to address data bus (AD15 to AD00), RD, and WR pins. 84 To Top / Lineup / Index MB90520 Series (2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Max. 0.05 30 ms * Due to repeated 4 -- ms operations Parameter Power supply rising time Power supply cut-off time Symbol Pin name Condition tR tOFF VCC VCC -- * : VCC must be kept lower than 0.2 V before power-on. Notes: * The above ratings are values for causing a power-on reset. * When HST is set to "L", apply power according to this table to cause a power-on reset irrespective of whether or not a power-on reset is required. * There are internal registers which can be initialized only by a power-on reset. Apply power according to this rating to ensure initialization of the registers. tR VCC 2.7 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC 0.2 V 0.2 V VSS It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 85 To Top / Lineup / Index MB90520 Series (3) Clock Timings (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Typ. Max. FC X0, X1 -- 3 -- 16 MHz 4.0 V to Clock frequency FC X0, X1 3 -- 10 MHz MB90F523 4.5 V FCL X0A, X1A -- 32.768 -- kHz -- tHCYL X0, X1 62.5 -- 333 ns 4.0 V to X0, X1 Clock cycle time tHCYL 100 -- 333 ns MB90F523 4.5 V X0A, X1A -- 30.5 -- s tLCYL Recommened PWH, X0 10 -- -- ns duty ratio of PWL 30% to 70% Input clock pulse width PWLH, X0A -- 15.2 -- s PWLL tCR, External clock Input clock rising/falling time X0, X0A -- -- 5 ns operation tCF When the main fCP -- 1.5 -- 16 MHz clock is used Internal operating clock 4.0 V to When the main fCP -- 1.5 -- 10 MHz frequency 4.5 V clock is used Subclock -- -- 8.192 -- kHz fLCP operation When the main tCP -- 62.5 -- 333 ns clock is used Internal operating clock cycle 4.0 V to When the main tCP -- 100 -- 333 ns time 4.5 V clock is used Subclock -- -- 122.1 -- s tLCP operation Frequency fluctuation rate f -- -- -- 5 %* locked * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + + f = | | x 100 (%) fO Center frequency fO - - The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)", thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). 86 To Top / Lineup / Index MB90520 Series * X0, X1 clock timing tHCYL 0.8 VCC X0 PWH tCF 0.8 VCC 0.2 VCC PWL tCR 0.2 VCC 0.8 VCC * X0A, X1A clock timing tLCYL 0.8 VCC X0A PWLH tCF 0.8 VCC 0.2 VCC PWLL tCR 0.2 VCC 0.8 VCC * PLL operation guarantee range (V) Power supply voltage VCC Relationship between internal operating clock frequency and power supply voltage MB90F523 guarantee range 5.5 4.5 4.0 3.3 3.0 MB90523 guarantee range PLL operation guarantee range MB90V520 guarantee range 1 3 10 8 Internal clock fCP 12 16 (MHz) Relationship between oscillating frequency, internal operating clock frequency, and power supply voltage (MHz) 16 Internal clock fCP 12 8 4 3 2 1 2 3 4 6 8 Oscillation clock FC 12 16 (MHz) Multiplied Multiplied Multiplied -by-3 -by-2 -by-4 Multiplied -by-1 Not multiplied 87 To Top / Lineup / Index MB90520 Series The AC ratings are measured for the following measurement reference voltages. * Input signal waveform Hystheresis input pin 0.8 VCC 0.2 VCC Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC * Output signal waveform Hystheresis input pin 2.4 VCC 0.8 VCC 88 To Top / Lineup / Index MB90520 Series (4) Recommended Resonator Manufactures * Sample application of ceramic resonator X0 R * X1 C1 C2 * Mask ROM product (MB90522, MB90523) Resonator manufacturer* Resonator CSA2.00MG040 CSA4.00MG040 Murata Mfg. Co., Ltd. CSA8.00MTZ CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.00 to 12.00 20.00 to 32.00 C1 (pF) 100 100 30 15 5 Built-in C2 (pF) 100 100 30 15 5 Built-in R Not required Not required Not required Not required Not required Not required Built-in Built-in Not required Built-in Built-in Not required (Continued) 89 To Top / Lineup / Index MB90520 Series (Continued) * Flash ROM product (MB90F523) Resonator Resonator manufacturer* CSA2.00MG040 CSA4.00MG040 Murata CSA8.00MTZ Mfg. Co., Ltd. CSA16.00MXZ040 CST32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.0 to 12.0 20.0 to 32.0 C1 (pF) 100 100 30 15 5 Built-in C2 (pF) 100 100 30 15 5 Built-in R Not required Not required Not required Not required Not required Not required Built-in Built-in Not required Built-in Built-in Not required Inquiry:Murata Mfg. Co., Ltd.. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.): TEL 65-758-4233 TDK Corporation * TDK Corporation of America Chicago Regional Office: TEL 1-708-803-6100 * TDK Electronics Europe GmbH Components Division: TEL 49-2102-9450 * TDK Singapore (PTE) Ltd.: TEL 65-273-5022 * TDK Hongkong Co., Ltd.: TEL 852-736-2238 * Korea Branch, TDK Corporation: TEL 82-2-554-6636 90 To Top / Lineup / Index MB90520 Series (5) Clock Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin Symbol name Condition Unit Remarks Min. Max. CLK VCC = 5.0 V 10% 62.5 -- ns tCYC VCC = 5.0 V 10% CLK 100 -- ns MB90F523 tCYC 4.0 V to 4.5 V tCHCL CLK VCC = 5.0 V 10% 20 -- ns VCC = 5.0 V 10% CLK 32 -- ns MB90F523 tCHCL 4.0 V to 4.5 V Parameter Cycle time CLK CLK tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V 91 To Top / Lineup / Index MB90520 Series (6) Ready Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRYHS RDY 45 -- ns -- RDY 0 -- ns tRYHH Parameter RDY setup time RDY hold time Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. 2.4 V CLK ALE 2.4 V RD/WR tRYHS RDY (wait inserted) 0.2 VCC tRYHS 0.2 VCC RDY (wait not inserted) 0.8 VCC 0.8 VCC tRYHH (7) Hold Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. HAK HAK -- 30 1 tCP* 1 tCP* 2 tCP* ns ns Parameter Symbol Pins in floating status tXHAL HAK time HAK pin valid time tHAHV * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HAK 0.8 V tXHAL Pins 2.4 V 0.8 V tHAHV 2.4 V 0.8 V 2.4 V High impedance 92 To Top / Lineup / Index MB90520 Series (8) UART (SCI) Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tSCYC 8 tCP* SCK0 to SCK4 -- ns SCK0 to SCK4, Internal shift clock - 80 80 ns tSLOV SOT0 to SOT4 mode SCK0 to SCK4, CL = 80 pF tIVSH 100 -- ns + 1 TTL for an SIN0 to SIN4 SCK0 to SCK4, output pin 60 -- ns tSHIX SIN0 to SIN4 tSHSL tSLSH tSLOV tIVSH tSHIX SCK0 to SCK4 SCK0 to SCK4 External shift clock mode SCK0 to SCK4, CL = 80 pF SOT0 to SOT4 + 1 TTL for an SCK0 to SCK4, output pin SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 4 tCP* 4 tCP* -- 60 60 -- -- 150 -- -- ns ns ns ns ns Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitor value connected to pins while testing. 93 To Top / Lineup / Index MB90520 Series * Internal shift clock mode SCK 0.8 V tSLOV SOT 2.4 V 0.2 V tSCYC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN * External shift clock mode SCK 0.2 VCC tSLOV SOT tSLSH 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN 94 To Top / Lineup / Index MB90520 Series (9) Timer Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. IN0, IN1 -- 4 tCP* -- ns Parameter Input pulse width Symbol tTIWH, tTIWL * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 0.8 VCC IN tTIWH 0.8 VCC 0.2 VCC 0.2 VCC tTIWL (10) Timer Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. OUT0 to OUT3, tTO -- 30 -- ns PPG0, PPG1 Parameter CLK TOUT transition time 2.4 V CLK tTO TOUT 2.4 V 0.8 V 95 To Top / Lineup / Index MB90520 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Condition Unit Min. Typ. Max. -- -- -- 8/10 -- bit -- -- -- -- 5.0 LSB -- -- -- -- 2.5 LSB -- VOT VFST -- -- IAIN VAIN -- -- IA Power supply current IAH IR Reference voltage supply current Offset between channels IRH -- -- AN0 to AN7 AN0 to AN7 -- -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 Supply current when CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- Supply current when CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- -- VCC = 5.0 V 10% at machine clock of 16 MHz VCC = 5.0 V 10% at machine clock of 16 MHz -- -- 1.9 LSB mV mV ns ns A V V V mA A A A Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling period Analog port input current Analog input voltage Reference voltage AVSS AVSS +0.5 LSB -3.5 LSB +4.5 LSB AVRH -6.5LSB 176 tCP* -- -- AVRL AVRL + 2.7 0 -- -- -- -- AVRH AVRH -1.5 LSB +1.5 LSB -- 64 tCP* -- -- -- -- 5 -- 400 -- -- -- 10 AVRH AVCC AVRH -2.7 -- 5 -- 5 -- -- -- 4 LSB * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 96 To Top / Lineup / Index MB90520 Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 3FE 3FD Actual conversion characteristics 0.5 LSB' {1 LSB x (N - 1) + 0.5 LSB} Digital output 004 003 002 001 VNT (mesured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB' AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB' 1 LSB' = (Theoretical value) AVRH - AVRL 1024 [V] Total error for digital output N = [LSB] VOT' (Theoretical value) = AVRL + 0.5 LSB' [V] VFST' (Theoretical value) = AVRH - 1.5 LSB' [V] VNT: Voltage at a transition of digital output from (N - 1) to N (Continued) 97 To Top / Lineup / Index MB90520 Series (Continued) Linearity error 3FF 3FE 3FD Actual conversion characteristics {1 LSB x (N - 1) + VOT'} N+1 VFST (mesured value) Actual conversion characteristics Differential linearity error Theoretical characteristics N Digital output Digital output 004 003 002 001 Theoretical characteristics VOT (mesured value) AVRL Analog input VNT (mesured value) Actual conversion characteristics N-1 V(N + 1)T (mesured value) VNT (mesured value) Actual conversion characteristics N-2 AVRH AVRL Analog input AVRH Linearity error of VNT - {1 LSB x (N - 1) + VOT} [LSB] digital output N = 1 LSB' Differential linearity error = of digital N 1 LSB = VFST - VOT V(N + 1)T - VNT 1 LSB' - 1 LSB [LSB] [V] 1022 VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH" 7. Notes on Using A/D Converter The impedance value of about 5 k or lower for the external circuit of analog input are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Block diagram of analog input circuit model Analog input RON C Comparator MB90523 RON: Approx. 1.5 k C: Approx. 3.0 pF MB90F523 RON: Approx. 3.0 k C: Approx. 65 pF Note: Listed values must be considered as standards. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 98 To Top / Lineup / Index MB90520 Series 8. D/A Converter Electrical Characteristics (AVCC = VCC = DVCC = 5.0 V 10%, AVSS = VSS = DVSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Symbol Pin name Min. Typ. Max. -- -- -- -- -- -- IDVR IDVRS -- DVCC DVCC DVCC -- -- -- -- -- -- -- -- -- -- -- VSS + 3.0 -- -- -- 8 -- -- -- 10 -- -- -- 20 -- 0.9 1.2 1.5 20 AVCC 300 10 -- bit LSB % LSB s Load capacitance: 20 pF V A A In sleep mode k Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance 99 To Top / Lineup / Index MB90520 Series s EXAMPLE CHARACTERISTICS (1) Power Supply Current (MB90523) ICC - VCC ICC (mA) 35 TA = +25C 30 25 20 15 10 5 3.0 4.0 ICC - TA ICC (mA) 35 VCC = 5.0 V 30 25 20 15 10 5 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz -20 +10 +40 +70 +100 TA (C) ICCL - VCC ICCL (A) 160 TA = +25C 140 120 100 80 60 40 20 3.0 4.0 5.0 6.0 VCC (V) 20 10 3.0 Fc = 8 kHz ICCLS (mA) 70 60 50 40 30 ICCS (mA) 10 9 8 7 6 5 4 3 2 1 -20 5.0 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 6.0 VCC (V) ICCS (mA) 10 9 8 7 6 5 4 3 2 1 3.0 ICCS - VCC TA = +25C Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 4.0 ICCS - TA 5.0 6.0 VCC (V) VCC = 5.0 V Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz +10 +40 +70 +100 TA (C) ICCLS - VCC TA = +25C Fc = 8 kHz 4.0 5.0 6.0 VCC (V) 100 To Top / Lineup / Index MB90520 Series ICC - Fc ICC (mA) 35 TA = +25C 30 25 20 15 10 5 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCS (mA) 10 9 8 7 6 5 4 3 2 1 4.0 6.0 8.0 12.0 16.0 Fc (MHz) ICCH (A) 10 9 8 Fc = 8 kHz 7 6 5 4 3 2 1 3.0 4.0 ICCT - TA ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 +40 +70 +100 TA (C) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCL (A) 10 9 8 7 6 5 4 3 2 1 -20 5.0 6.0 VCC (V) 3.0 4.0 ICCS - Fc TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 6.0 8.0 ICCH - VCC 12.0 16.0 Fc (MHz) ICCT - VCC ICCT (A) 20 18 16 14 12 10 8 6 4 2 TA = +25C TA = +25C 4.0 ICCH - TA 5.0 6.0 VCC (V) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +10 +40 +70 +100 TA (C) 101 To Top / Lineup / Index MB90520 Series ICCL - TA ICCL (A) 20 18 16 14 12 10 8 6 4 2 -20 +10 +40 +70 +100 TA (C) ICCLS (A) 14 12 10 8 6 4 2 -20 ICCLS - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +10 +40 +70 +100 TA (C) (2) Power Supply Current (MB90F523) ICC - VCC ICC (mA) 140 TA = +25C 120 100 80 60 40 20 Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 35 Fc = 16 MHz 30 25 20 15 10 5 3.0 4.0 ICC - TA ICCS (mA) 40 35 Fc = 16 MHz Fc = 12.5 MHz 60 40 20 Fc = 10 MHz Fc = 8 MHz 15 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 10 5 -20 +10 +40 +70 +100 TA (C) -20 +10 +40 +70 30 25 20 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz +100 TA (C) 5.0 6.0 VCC (V) 3.0 4.0 ICCS - TA 5.0 Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz Fc = 16 MHz ICCS (mA) 40 TA = +25C ICCS - VCC 6.0 VCC (V) ICC (mA) 120 100 80 VCC = 5.0 V VCC = 5.0 V 102 To Top / Lineup / Index MB90520 Series ICCS - VCC ICCLS (A) 200 180 160 140 120 100 80 60 40 20 3.0 4.0 5.0 6.0 VCC (V) ICCS - Fc ICCS (mA) 40 TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V 60 40 20 VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 20 15 10 5 4.0 8.0 12.0 ICCH - VCC ICCH (A) 10 TA = +25C 40 Fc = 8 kHz 30 9 8 7 6 5 20 4 3 10 2 1 3.0 4.0 5.0 6.0 VCC (V) 3.0 4.0 5.0 6.0 VCC (V) 35 30 25 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 16.0 Fc (MHz) Fc = 8 MHz TA = +25C ICC - Fc ICC (mA) 120 TA = +25C 100 80 4.0 8.0 12.0 16.0 Fc (MHz) ICCT - VCC ICCT (A) 50 TA = +25C 103 To Top / Lineup / Index MB90520 Series ICCT - TA ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 +40 +70 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +100 TA (C) ICCLS - TA ICCLS (A) 20 18 16 14 12 10 8 6 4 2 -20 +10 +40 +70 +100 TA (C) ICCH (A) 10 9 8 7 6 5 4 3 2 1 -20 ICCH - TA +10 +40 +70 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +100 TA (C) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 104 To Top / Lineup / Index MB90520 Series s INSTRUCTIONS (340 INSTRUCTIONS) Table 1 Item Mnemonic Description of items in instruction list Description English upper case and symbol: Described directly in assembler code. English lower case: Converted in assembler code. Number of letters after English lower case: Describes bit width in code. Describes number of bytes. Describes number of cycles. m : For branch operation n : For non-branch operation For other letters in other items, refer to table 4. Describes the number of times the register is accessed during instruction execution. Used to calculate a corrective value for CPU intermittent operation. Describes correction value for calculating number of actual cycles (refer to table 5). Number of actual cycles is calculated by adding values in the ~section and section B. Describes operation of instructions. Describes a special operation to the upper 8-bit of the lower 16-bit of the accumulator. Z : Transfer 0. X : Sign-extend and transfer. - : No transmission Describes a special operation to the upper 16-bit of the accumulator. * : Transmit from AL to AH. - : No transfer. Z : Transfer 00H to AH. X : Sign-extend AL and transfer 00H or FFH to AH. Describe status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry) flags. * : Changes after execution of instruction. - : No changes. S : Set after execution of instruction. R : Reset after execution of instruction. # ~ RG B Operation LH AH I S T N Z V C RMW Describes whether or not the instruction is a read-modify-write type (a data is read out from memory etc. in single cycle, and the result is written into memory etc.). * : Read-modify-write instruction - : Not read-modify-write instruction Note: Not used to addresses having different functions for reading and writing operations. * Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number 105 To Top / Lineup / Index MB90520 Series of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles. Table 2 Item A Description of Symbols in Instruction Table Description 32-bit accumlator The bit length is dependent on the instructions to be used. Byte : Lower 8-bit of AL Word :16-bit of AL Long : AL: 32-bit of AH Upper 16-bit of A Lower 16-bit of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Specify shortened direct address. Specify direct address. Specify physical direct address. bit0 to bit15 of addr24 bit16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data calculated by sign-extending an 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset value AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp (Continued) 106 To Top / Lineup / Index MB90520 Series (Continued) Item vct4 vct8 ( )b rel ear eam rlst Vector number (0 to 15) Vector number (0 to 255) Bit address Specify PC relative branch. Specify effective address (code 00 to 07). Specify effective address (code 08 to 1F). Register allocation Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Symbol RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Field Address type Register direct ea corresponds to byte, word, and long word from left respectively. -- Number of bytes in address extension block Description Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 0 0 2 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address Note: Number of bytes for address extension corresponds to "+" in the # (number of bytes) the number of bytes in detailed instruction rules part in the instruction table. 107 To Top / Lineup / Index MB90520 Series Table 4 Code Number of Execution Cycles for Effective Address in Addressing Modes (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for addressing modes Listed in instruction table 2 4 2 2 4 4 2 1 Number of register accesses for addressing modes Listed in instruction table 1 2 1 1 2 2 0 0 00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F Note: (a) is used for ~ (number of cycles) and B (correction value) detailed instruction rules in instruction table. Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles (b) byte Operand Internal register Internal memory even address Internal memory odd address External data bus 16-bit even address External data bus 16-bit odd address External data bus 8-bit (c) word (d) long Number of Number of Number of Number of Number of Number of cycles access cycles access cycles access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4 Notes: * (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table. * When the external bus is used, cycles for wait insertion for the ready input and automatic ready operation must be added. Table 6 Correction Value for Number of Cycles for Calculating Number of Program Fetch Cycles Instruction Internal memory External data bus 16-bit External data bus 8-bit Byte boundary -- -- +3 Word boundary +2 +3 -- Notes: * When the external bus is used, cycles for wait insertion for the ready input and automatic ready operation must be added. * Because execution of instruction is not delayed for all program fetch operations, use this value to calculate the worst case. 108 To Top / Lineup / Index MB90520 Series Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH # ~ Transmission Instruction (Byte) [41 Instructions] RG B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi) + disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RMW 3 2 A, dir 4 3 A, addr16 2 1 A, Ri 2 2 A, ear 2 + 3 + (a) A, eam 3 2 A, io 2 2 A, #imm8 3 2 A, @A 10 A, @RLi + disp8 3 1 1 A, #imm4 3 2 A, dir 4 3 A, addr16 2 2 A, Ri 2 2 A, ear 2 + 3 + (a) A, eam 3 2 A, io 2 2 A, #imm8 3 2 A, @A 5 A, @RWi + disp8 2 10 A, @RLi + disp8 3 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi + disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 Z Z Z Z Z Z Z Z Z Z * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - X X X X X X X X byte (A) ((RWi) + disp8) X byte (A) ((RLi) + disp8) X byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) + disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) - - - - - - - - - - - - - - - - - Z Z - - 4 2 2 + 5 + (a) 7 2 2 + 9 + (a) 0 2 0 2 x (b) 0 4 2 2 x (b) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 109 To Top / Lineup / Index MB90520 Series Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW Transmission Instruction (Word, Long) [38 Instructions] ~ RG # B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 x (c) 0 2 x (c) 0 (d) 0 0 (d) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RMW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 2 3 3 4 1 1 1 2 2 2 2 + 3 + (a) 2 3 2 3 3 2 A, @RWi + disp8 2 5 A, @RLi + disp8 3 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 - - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear1) (A) long (eam1) (A) - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOVW MOVW MOVW MOVW MOVW MOVW MOVW 2 3 1 1 2 2+ 2 MOVW @RWi + disp8, A 2 MOVW @RLi + disp8, A 3 MOVW RWi, ear 2 MOVW RWi, eam 2+ MOVW ear, RWi 2 MOVW eam, RWi 2+ MOVW RWi, #imm16 3 MOVW io, #imm16 4 MOVW ear, #imm16 4 MOVW eam, #imm16 4 + MOVW @AL, AH /MOVW @A, T XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A, ear A, eam RWi, ear RWi, eam A, ear A, eam A, #imm32 ear, A eam, A 2 dir, A addr16, A SP A , RWi, A ear, A eam, A io, A 2 4 2 + 5 + (a) 2 7 2 + 9 + (a) 2 4 2 2 + 5 + (a) 0 5 3 0 2 4 2 2 + 5 + (a) 0 Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 110 To Top / Lineup / Index MB90520 Series Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 2 3 4 + (a) 2 3 5 + (a) 3 4 + (a) 2 3 4 + (a) 2 3 5 + (a) 3 4 + (a) Add/Subtract (Byte, Word, Long) [42 Instructions] B Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) LH AH RG I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * RMW 0 0 0 (b) 1 0 0 (b) 2 0 0 2 x (b) 0 0 1 0 0 (b) 0 0 0 0 0 (b) 1 0 0 (b) 2 0 0 2 x (b) 0 0 1 0 0 (b) 0 0 0 0 1 0 0 (c) 0 0 2 0 0 2 x (c) 1 0 0 (c) 0 0 1 0 0 (c) 0 0 2 0 0 2 x (c) 1 0 0 (c) 2 0 0 2 0 0 0 (d) 0 0 (d) 0 byte (A) (AH) + (AL) + (C) (decimal) byte (A) (AH) - (AL) - (C) (decimal) Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - - ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL A, ear A, eam word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32 2 6 2 + 7 + (a) 4 A, #imm32 5 2 6 A, ear 2 + 7 + (a) A, eam 4 A, #imm32 5 Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 111 To Top / Lineup / Index MB90520 Series Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam # Increment/Decrement (Byte, Word, Long) [12 Instructions] ~ RG B Operation LH AH I - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C - - - - - - - - - - - - RMW 2 2 2 0 byte (ear) (ear) +1 2 + 5 + (a) 0 2 x (b) byte (eam) (eam) +1 2 3 2 0 byte (ear) (ear) -1 2 + 5 + (a) 0 2 x (b) byte (eam) (eam) -1 2 3 2 0 word (ear) (ear) +1 2 + 5 + (a) 0 2 x (c) word (eam) (eam) +1 2 3 2 0 word (ear) (ear) -1 2 + 5 + (a) 0 2 x (c) word (eam) (eam) -1 2 7 4 0 long (ear) (ear) +1 2 + 9 + (a) 0 2 x (d) long (eam) (eam) +1 2 7 4 0 long (ear) (ear) -1 2 + 9 + (a) 0 2 x (d) long (eam) (eam) -1 - - - - - - - - - - - - - - - - - - - - - - - - - * - * - * - * - * - * DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # ~ RG Compare (Byte, Word, Long) [11 Instructions] B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 word (A) - (ear) word (A) - (eam) word (A) - imm32 LH AH I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C * * * * * * * * * * * RMW 1 1 2 2 2 + 3 + (a) 2 2 0 1 0 0 0 1 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A 1 1 A, ear 2 2 A, eam 2 + 3 + (a) A, #imm16 3 2 A, ear 2 6 2 A, eam 2 + 7 + (a) 0 A, #imm32 5 3 0 Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 112 To Top / Lineup / Index MB90520 Series Table 12 Mnemonic DIVU DIVU DIVU DIVUW DIVUW A A, ear # 1 2 ~ *1 *2 Unsigned Multiply/Division (Word, Long) [11 Instructions] RG B 0 1 0 1 0 0 Operation LH AH I - - - - - S - - - - - T - - - - - N - - - - - Z - - - - - V * * * * * C * * * * * RMW A, eam 2 + *3 A, ear A, eam 2 2+ *4 *5 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A) - - - - - - - - - - - - - - - MULU MULU MULU MULUW MULUW MULUW A 1 A, ear 2 A, eam 2 + A 1 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *1: Set to 3 when the division-by-0, 7 for an overflow, and 15 for normal operation. *2: Set to 4 when the division-by-0, 8 for an overflow, and 16 for normal operation. *3: Set to 6 + (a) when the division-by-0, 9 + (a) for an overflow, and 19 + (a) for normal operation. *4: Set to 4 when the division-by-0, 7 for an overflow, and 22 for normal operation. *5: Set to 6 + (a) when the division-by-0, 8 + (a) for an overflow, and 26 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero. *9: Set to 4 when byte (ear) is zero, 8 when byte (ear) is not zero. *10: Set to 5 + (a) when byte (eam) is zero, 9 + (a) when byte (eam) is not zero. *11: Set to 3 when word (AH) is zero, 11 when word (AH) is not zero. *12: Set to 4 when word (ear) is zero, 12 when word (ear) is not zero. *13: Set to 5 + (a) when word (eam) is zero, 13 + (a) when word (eam) is not zero. Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 113 To Top / Lineup / Index MB90520 Series Table 13 Mnemonic DIV DIV DIV DIVW DIVW A A, ear # 2 2 ~ *1 *2 Signed Multiplication/Division (Word, Long) [11 Instructions] RG B 0 1 0 1 0 0 Operation LH AH I - - - - - S - - - - - T - - - - - N - - - - - Z - - - - - V * * * * * C * * * * * RMW A, eam 2 + *3 A, ear A, eam 2 2+ *4 *5 word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A) Z Z Z - - - - - - - - - - - - MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4: A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 114 To Top / Lineup / Index MB90520 Series Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ RG Logic 1 (Byte, Word) [39 Instructions] B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RMW 2 2 2 3 2 + 4 + (a) 2 3 2 + 5 + (a) 2 2 2 3 2 + 4 + (a) 2 3 2 + 5 + (a) 2 2 2 3 2 + 4 + (a) 2 3 2 + 5 + (a) 1 2 2 3 2 + 5 + (a) 0 0 1 0 0 (b) 2 0 0 2 x (b) 0 0 1 0 0 (b) 2 0 0 2 x (b) 0 0 1 0 0 (b) 2 0 0 2 x (b) 0 0 2 0 0 2 x (b) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 x (c) 0 0 0 (c) 0 2 x (c) 0 0 0 (c) 0 2 x (c) 0 0 2 x (c) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - * A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2 + 4 + (a) ear, A 2 3 eam, A 2 + 5 + (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2 + 4 + (a) ear, A 2 3 eam, A 2 + 5 + (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2 + 4 + (a) ear, A 2 3 eam, A 2 + 5 + (a) A 1 2 ear 2 3 eam 2 + 5 + (a) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 115 To Top / Lineup / Index MB90520 Series Table 15 Mnemonic ANDL ANDL ORL ORL XORL XORL A, ear A, eam A, ear A, eam A, ear A, eam # ~ RG Logic 2 (Long) [6 Instructions] Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH B 0 (d) 0 (d) 0 (d) I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C - - - - - - RMW 2 6 2 2 + 7 + (a) 0 2 6 2 2 + 7 + (a) 0 2 6 2 2 + 7 + (a) 0 - - - - - - - - - - - - - - - - - - Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2 RG Sign Reverse (Byte, Word) [6 Instructions] B 0 Operation byte (A) 0 - (A) LH AH I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C * * * * * * RMW 0 X - - - - - - - - - - - - - * - - * 2 3 2 0 byte (ear) 0 - (ear) 2 + 5 + (a) 0 2 x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A) NEGW A NEGW ear NEGW eam 2 3 2 2 + 5 + (a) 0 0 word (ear) 0 - (ear) 2 x (c) word (eam) 0 - (eam) Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 Normalize Instruction (Long) [1 Instruction] B 0 Operation long (A) Shift to where "1" is originally located byte (R0) Number of shifts in the operation LH AH I - S - T - N - Z * V - C - RMW - - - *1: Set to 4 when the accumulator is all "0", otherwise set to 6 + (R0). Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 116 To Top / Lineup / Index MB90520 Series Table 18 Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0 # 2 2 2 2+ 2 2+ 2 2 2 ~ 2 2 3 5 + (a) RG Shift Type Instruction (Byte, Word, Long) [18 Instructions] B 0 0 Operation byte (A) With right-rotate carry byte (A) With left-rotate carry byte (ear) With right-rotate carry byte (eam) With right-rotate carry byte (ear) With left-rotate carry byte (eam) With left-rotate carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Arithmetic right barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) LH AH I - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * RMW 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * - - - - - - - - - - - - 3 5 + (a) 2 0 0 2 x (b) 2 0 0 2 x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2 ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 2 2 2 ** *R -* * * - * * - * * * * * * *1: Set to 6 when R0 is 0, otherwise 5 + (R0). *2: Set to 6 when R0 is 0, otherwise 6 + (R0). Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 117 To Top / Lineup / Index MB90520 Series Table 19 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP CALLP CALLP *1: *2: *3: *4: *5: *6: *7: @A Branch 1 [31 Instructions] Operation LH AH # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 x (c) (c) 2 x (c) 2 x (c) *2 2 x (c) I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RMW Branch if (Z) = 1 Branch if (Z) = 0 Branch if (C) = 1 Branch if (C) = 0 Branch if (N) = 1 Branch if (N) = 0 Branch if (V) = 1 Branch if (V) = 0 Branch if (T) = 1 Branch if (T) = 0 Branch if (V) xor (N) = 1 Branch if (V) xor (N) = 0 Branch if ((V) xor (N)) or (Z) = 1 Branch if ((V) xor (N)) or (Z) = 0 Branch if (C) or (Z) = 1 Branch if (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - addr16 @ear @eam @ear *3 @eam *3 addr24 1 2 3 3 2 3 2 + 4 + (a) 2 5 2 + 6 + (a) 4 4 word (PC) (ear), (PCB) (ear + 2) word (PC) (eam), (PCB) (eam + 2) @ear *4 2 6 @eam *4 2 + 7 + (a) addr16 *5 3 6 1 7 #vct4 *5 2 10 @ear *6 @eam *6 addr24 *7 2 + 11 + (a) 0 4 10 0 word (PC) ad24 0 - 15, (PCB) ad24 16 - 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 - 15 (PCB) (ear) 16 - 23 word (PC) (eam) 0 - 15 (PCB) (eam) 16 - 23 word (PC) ad24 0 - 15, (PCB) ad24 16 - 23 Set to 4 when branch is executed, and 3 when branch is not executed. (b) + 3 x (c) Reads (word) of the branch destination address. W pushes to stack (word), and R reads (word) of the branch destination address. Pushes to stack (word). W pushes to stack (long), and R reads (long) of the branch destination address. Pushes to stack (long). Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 118 To Top / Lineup / Index MB90520 Series Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE Branch 2 (Byte) [19 Instructions] Operation Branch if word (A) imm16 LH AH # ~ RG 0 0 1 0 1 0 2 B 0 0 0 (b) 0 (c) 0 I - - - - - - - - - - R R R R * - S - - - - - - - - - - S S S S * - T - - - - - - - - - - - - - - * - N * * * * * * * * * * - - - - * - Z * * * * * * * * * * - - - - * - V * * * * * * * * * * - - - - * - C * * * * * * - - - - - - - - * - RMW 3 *1 4 *1 *2 *3 *4 *3 Branch if byte (A) imm8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - * - - - - - - 4 4+ CWBNE ear, #imm16, rel 5 CWBNE eam, #imm16, rel*10 5 + eam, #imm8, rel*10 ear, #imm8, rel Branch if byte (ear) imm8 Branch if byte (eam) imm8 Branch if word (ear) imm16 Branch if word (eam) imm16 DBNZ DBNZ ear, rel eam, rel 3 *5 3 + *6 3 *5 3 + *6 2 3 4 1 1 2 20 16 17 20 17 6 byte (ear) = (ear) - 1, Branch if (ear) 0 2 2 x (b) byte (eam) = (eam) - 1, Branch if (eam) 0 2 word (ear) = (ear) - 1, Branch if (ear) 0 2 2 x (c) word (eam) = (eam) - 1, Branch if (eam) 0 0 0 0 0 0 0 8 x (c) 6 x (c) 6 x (c) 8 x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Stores old frame pointer in the beginning of the function, set new frame pointer, and reserves local pointer area Restore old frame pointer from stack in the end of the function Return from subroutine Return from subroutine 0 DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24 #imm8 UNLINK 1 5 0 (c) - - - - - - - - - - RET *8 RETP *9 1 1 4 6 0 0 (c) (d) - - - - - - - - - - - - - - - - - - - - *1: Set to 5 when branch is executed, and 4 when branch is not executed. *2: Set to 13 when branch is executed, and 12 when branch is not executed. *3: Set to 7 + (a) when branch is executed, and 6 + (a) when branch is not executed. *4: Set to 8 when branch is executed, and 7 when branch is not executed. *5: Set to 7 when branch is executed, and 6 when branch is not executed. *6: Set to 8 + (a) when branch is executed, and 7 + (a) when branch is not executed. *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Return from stack (word). *9: Return from stack (long). *10: Do not use the addressing mode of RWj + in CBNE/CWBNE instruction. Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 119 To Top / Lineup / Index MB90520 Series Table 21 Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR MOV MOV Miscellaneous Control Types (Byte, Word, Long) [28 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2 RG 0 0 0 +& 0 0 0 +& B (c) (c) (c) *4 (c) (c) (c) *4 Operation LH AH # 1 1 1 2 1 1 1 2 1 2 2 I - - - - - - * - * * * - - - - - - - - - - - - - - - - - STNZVC - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - RMW A AH PS rlst A AH PS rlst @A CCR, #imm8 CCR, #imm8 word (SP) (SP) - 2, ((SP)) (A) - word (SP) (SP) - 2, ((SP)) (AH) - word (SP) (SP) - 2, ((SP)) (PS) - (PS) (PS) - 2n, ((SP)) (rlst) - - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - word (A) ((SP)), (SP) (SP) + 2 word (AH) ((SP)), (SP) (SP) + 2 word (PS) ((SP)), (SP) (SP) + 2 (rlst) ((SP)), (SP) (SP) + 2n - - - - - 0 6 x (c) Context switch instruction 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (CCR) (CCR) and imm8 - byte (CCR) (CCR) or imm8 - byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam - - - - - - RP #imm8 2 , ILM, #imm8 2 MOVEA MOVEA MOVEA MOVEA RWi, ear 2 3 RWi, eam 2 + 2 + (a) A, ear 2 1 A, eam 2 + 1 + (a) 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1 ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A word (SP) (SP) + ext (imm8) - - word (SP) (SP) + imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no change in flag Prefix for common register bank Z - - - - - - - - *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (number of POPs) + 2 x (the number of the last register to be POPed), 7 if rlst = 0(no transfer registers) *3: 29 + 3 x (number of PUSHes) - 3 x (the number of the last register to be PUSHed), 8 if rlst = 0(no transfer registers) *4: (Number of POPs) x (c), or (number of PUSHes) x (c) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 120 To Top / Lineup / Index MB90520 Series Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS SBBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bpvrel addr16:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 RG 0 0 0 Bit Manipulation Instruction [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I - - - - - - - - - - - - - - - - - - - - - STNZVC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RMW Z Z Z - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - 0 2 x (b) bit (dir:bp) b (A) 0 2 x (b) bit (addr16:bp) b (A) 0 2 x (b) bit (io:bp) b (A) 0 2 x (b) bit (dir:bp) b 1 0 2 x (b) bit (addr16:bp) b 1 0 2 x (b) bit (io:bp) b 1 0 2 x (b) bit (dir:bp) b 0 0 2 x (b) bit (addr16:bp) b 0 0 2 x (b) bit (io:bp) b 0 0 0 0 0 0 0 (b) (b) (b) (b) (b) (b) Branch if (dir:bp) b = 0 Branch if (addr16:bp) b = 0 Branch if (io:bp) b = 0 Branch if (dir:bp) b = 1 Branch if (addr16:bp) b = 1 Branch if (io:bp) b = 1 0 2 x (b) Branch if (addr16:bp) b = 1, bit = 1 - 0 0 *5 *5 Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 - - WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5: Set to 8 when branch is executed, and 7 when branch is not executed. Set to 7 when branch is executed, and 6 when branch is not executed. 10 if conditions are met, 9 when conditions are not met. Indeterminate times Until conditions are met Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 121 To Top / Lineup / Index MB90520 Series Table 23 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instruction (Byte, Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 RG B 0 0 0 0 0 0 Operation byte (A) 0 - 7 (A) 8 - 15 word (AH) (AL) byte sign-extension word sign-extension byte zero-extension word zero-extension LH AH I - - - - - - S - - - - - - T - - - - - - N - - * * R R Z - - * * * * V - - - - - - C - - - - - - RMW 0 0 0 0 0 0 - - X - Z - - * - X - Z - - - - - - Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ *2 *2 *1 *1 RG String Instruction [10 Instructions] Operation LH AH B I - - - - - - - - - - S - - - - - - - - - - T - - - - - - - - - - N - - * * * - - * * * Z - - * * * - - * * * V - - * * - - - * * - C - - * * - - - * * - RMW *5 *3 byte transfer @AH + @AL +, Counter = RW0 *5 *3 byte transfer @AH - @AL -, Counter = RW0 *5 *4 byte search (@AH +) - AL, Counter = RW0 *5 *4 byte search (@AH -) - AL, Counter = RW0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 6m + 6 *5 *3 byte fill @AH + AL, Counter = RW0 *2 *2 *1 *1 *8 *6 word transfer @AH + @AL +, Counter = RW0 *8 *6 word transfer @AH - @AL -, Counter = RW0 *8 *7 word search (@AH +) - AL, Counter = RW0 *8 *7 word search (@AH -) - AL, Counter = RW0 MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI 2 SCWEQD FILSW/FILSWI 2 2 6m + 6 *8 *6 word fill @AH + AL, Counter = RW0 m: RW0 value (counter value) n: Number of loops *1: 5 when RW0 is 0, 4 + 7 x (RW0) when count out, and 7 x n + 5 when matched *2: 5 when RW0 is 0, otherwise 4 + 8 x (RW0) *3: To access different areas for source (b) x (RW0) + (b) x (RW0) and source destination, calculate item (b) independently. *4: (b) x n *5: 2 x (RW0) *6: To access different areas for source (c) x (RW0) + (c) x (RW0) and source destination, calculate item (b) independently. *7: (c) x n *8: 2 x (RW0) Note: For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles." 122 Table 25 30 MOV @RL0 2-byte Instruction Map [Byte 1 = 6 FH] 60 70 80 90 A0 B0 C0 D0 E0 F0 00 + d8, A @RL0 + d8 10 MOV A, 20 40 50 +0 MOV MOV MOVX A, A, DTB DTB, A @RL0 + d8 +1 MOV @RL1 MOV MOV A, ADB ADB, A + d8, A @RL1 + d8 +2 MOV MOV MOVX A, A, SSB SSB, A @RL1 + d8 MOV A, +3 MOV @RL2 MOV MOV A, USB USB, A + d8, A @RL2 + d8 +4 MOV MOV MOVX A, A, DPR DPR, A @RL2 + d8 MOV A, +5 MOV @RL3 MOV MOV A, @A @AL, AH + d8, A @RL3 + d8 +6 MOV MOVX MOVX A, A, @A @RL3 + d8 A, PCB MOV A, +7 MOVW @RL ROLC MOVW A, @RL0 + d8 RORC MUL A MULW A MOVW @RL A 0 + d8, A A +8 +9 1 + d8, A @RL1 + d8 +A A MOVW A, DIVU +B +C LSLW LSLL LSL MOVW @RL MOVW A, A, R0 A, R0 A, R0 2 + d8, A @RL2 + d8 +D MOVW MOVW NRML A, @A @AL, AH A, R0 +E ASRW ASRL ASR MOVW @RL MOVW A, A, R0 A, R0 A, R0 3 + d8, A @RL3 + d8 MB90520 Series +F LSRW LSRL LSR A, R0 A, R0 A, R0 To Top / Lineup / Index 123 124 Table 26 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 ea Instruction (9) [Byte 1 = 78 H] MUL A, @RW0 + d16 00 10 20 +0 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R0 @RW0 + d8 A, RW0 @RW0 + d8 A, R0 @RW0 + d8 A, RW0 @RW0 + d8 A, R0 @RW0 + d8 A, RW0 @RW0 + d8 A, R0 @RW0 + d8 A, RW0 @RW0 + d8 +1 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R1 @RW1 + d8 A, RW1 @RW1 + d8 A, R1 @RW1 + d8 A, RW1 @RW1 + d8 A, R1 @RW1 + d8 A, RW1 @RW1 + d8 A, R1 @RW1 + d8 A, RW1 @RW1 + d8 +2 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R2 @RW2 + d8 A, RW2 @RW2 + d8 A, R2 @RW2 + d8 A, RW2 @RW2 + d8 A, R2 @RW2 + d8 A, RW2 @RW2 + d8 A, R2 @RW2 + d8 A, RW2 @RW2 + d8 MB90520 Series +3 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R3 @RW3 + d8 A, RW3 @RW3 + d8 A, R3 @RW3 + d8 A, RW3 @RW3 + d8 A, R3 @RW3 + d8 A, RW3 @RW3 + d8 A, R3 @RW3 + d8 A, RW3 @RW3 + d8 +4 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R4 @RW4 + d8 A, RW4 @RW4 + d8 A, R4 @RW4 + d8 A, RW4 @RW4 + d8 A, R4 @RW4 + d8 A, RW4 @RW4 + d8 A, R4 @RW4 + d8 A, RW4 @RW4 + d8 +5 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R5 @RW5 + d8 A, RW5 @RW5 + d8 A, R5 @RW5 + d8 A, RW5 @RW5 + d8 A, R5 @RW5 + d8 A, RW5 @RW5 + d8 A, R5 @RW5 + d8 A, RW5 @RW5 + d8 +6 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R6 @RW6 + d8 A, RW6 @RW6 + d8 A, R6 @RW6 + d8 A, RW6 @RW6 + d8 A, R6 @RW6 + d8 A, RW6 @RW6 + d8 A, R6 @RW6 + d8 A, RW6 @RW6 + d8 +7 MULU MULUW MULW DIVU DIVUW DIVW MULU A, MUL A, DIVU A, DIVUW A, DIV DIV A, DIVW A, MULUW A, MUL MULW A, A, R7 @RW7 + d8 A, RW7 @RW7 + d8 A, R7 @RW7 + d8 A, RW7 @RW7 + d8 A, R7 @RW7 + d8 A, RW7 @RW7 + d8 A, R7 @RW7 + d8 A, RW7 @RW7 + d8 MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 +8 MUL A, @RW1 + d16 MULU MULUW MULU A, MULUW A, MUL A, @RW0 @RW0 + d16 A, @RW0 @RW0 + d16 A, @RW0 +9 MUL A, @RW2 + d16 MULU MULUW MULU A, MULUW A, MUL A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 A, @RW1 @RW1 + d16 MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 +A MUL A, @RW3 + d16 MULU MULUW MULU A, MULUW A, MUL A, @RW2 @RW2 + d16 A, @RW2 @RW2 + d16 A, @RW2 +B MULUW A, MUL MULU MULUW MULU A, MULUW A, MUL A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 MUL A, MULW A, MULW DIVU DIVUW DIVW DIVU A, DIVUW A, DIV DIV A, DIVW A, MULW A, A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 A, @RW3 @RW3 + d16 MULW DIVU DIVU A, DIVU DIVUW DIVUW A, DIV DIV A, A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 +C MULUW A, MUL MULU MULU A, MULUW DIVW DIVW A, A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 A, @RW0 + @RW0 + RW7 +D MULUW A, MUL MULU MUL A, MUL A, MULW MULU A, MULUW MULW MULW A, DIVU A, DIVU DIVU A, DIVUW DIVUW A, DIVUW A, DIV DIV A, A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 DIVW DIVW A, A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 A, @RW1 + @RW1 + RW7 +E MULUW A, MUL MULU MULU A, MULUW MULW A, DIVUW DIV DIV A, A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 DIVW DIVW A, A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 A, @RW2 + @PC + d16 To Top / Lineup / Index +F addr16 A, @RW3 + MULU MULU A, MULUW MUL A, MULW A, @RW3 + MULW A, A, @RW3 + addr16 A, @RW3 + addr16 DIVU DIVU A, DIVUW A, DIV DIV A, DIVW A, DIVUW DIVW addr16 A, @RW3 + addr16 A, @RW3 + addr16 A, @RW3 + addr16 A, @RW3 + addr16 To Top / Lineup / Index MB90520 Series s ORDERING INFORMATION Part number MB90523PFF-G MB90522PFF-G MB90F523PFF-G MB90523PFV-G MB90522PFV MB90F523PFV-G Package 120-pin Plastic LQFP (FPT-120P-M05) 120-pin Plastic QFP (FPT-120P-M13) Remarks 125 To Top / Lineup / Index MB90520 Series s PACKAGE DIMENSIONS 120-pin Plastic LQFP (FPT-120P-M05) 16.000.20(.630.008)SQ 90 14.000.10(.551.004)SQ 61 1.50 -0.10 +.008 .059 -.004 +0.20 (Mounting height) 0.100.10 (STAND OFF) (.004.004) 91 60 Details of "A" part 11.60 (.457) REF 15.00 (.591) NOM 0.15(.006) 0.15(.006) 0.10(.004)MAX 0.36(.014)MAX 1 PIN INDEX 120 31 "A" LEAD No. 1 Details of "B" part 30 0.40(.0157)TYP 0.14 -0.03 +.003 .006 -.001 +0.08 0.065(.003) M 0.127 -0.02 +.002 .005 -.001 0 "B" 10 +0.05 0.10(.004) 0.500.20 (.020.008) C 1995 FUJITSU LIMITED F120006S-2C-3 Dimensions in mm (inches) 120-pin Plastic QFP (FPT-120P-M13) 22.600.20(.890.008)SQ 20.000.10(.787.004)SQ 3.85(.152)MAX (Mounting height) 61 90 0.05(.002)MIN (STAND OFF) 60 91 14.50 (.571) REF 21.60 (.850) NOM Details of "A" part 0.15(.006) 0.15(.006) INDEX 0.15(.006)MAX 0.40(.016)MAX "A" 1 30 120 31 Details of "B" part 0.1250.05 (.005.002) 0 10 LEAD No. 0.50(.0197) 0.200.10 (.008.004) 0.08(.003) M 0.500.20(.020.008) 0.10(.004) "B" C 1995 FUJITSU LIMITED F120013S-2C-3 Dimensions in mm (inches) 126 To Top / Lineup / Index MB90520 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9808 (c) FUJITSU LIMITED Printed in Japan 127 |
Price & Availability of MB90523
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